Shielded Gate MOSFET Trench Formation via CMP Planarization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional fabrication processes for trench-gated MOSFETs are complex and prone to errors due to multiple masking steps, leading to variations in substrate topography and electrical performance issues such as drain-to-source resistance and charge, necessitating a cost-effective and defect-minimizing approach.
Innovation Solution
A single masking/etching process is used to simultaneously form active gate trenches and wider gate runner trenches, with chemical mechanical planarization (CMP) techniques to achieve a planar surface and ensure uniformity, reducing misalignment and material deposition challenges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple masking steps are used to form complex structures, then device functionality is achieved, but manufacturing precision deteriorates due to mask misalignment errors
Solution Approach 1:
The patent combines multiple masking operations into a single masking step. Specifically, it uses one mask to define both the active gate trenches and the gate runner trench simultaneously, eliminating the need for separate masking steps that would introduce alignment errors. This merging approach maintains device functionality while significantly improving manufacturing precision.
2Ease of manufacture
If conventional fabrication processes are used, then device structure is formed, but device complexity increases leading to more process errors
Solution Approach 1:
The patent simplifies the fabrication process by merging the formation of active gate trenches and gate runner trenches into a single etching step using one mask. This reduces the number of process steps from multiple masking and etching operations to just one, thereby decreasing device complexity in terms of manufacturing while maintaining the required structural functionality.
3Ease of manufacture
If substrate surface topography varies, then trench formation is achieved, but manufacturing precision deteriorates due to non-uniform material deposition
Solution Approach 1:
The patent performs preliminary planarization of the substrate surface before trench formation and material deposition. By creating a flat substrate surface in advance, the process ensures that subsequent material deposition and photolithography steps occur on a uniform plane, eliminating the non-uniformity that would result from varying topography while still enabling trench formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes defects and enhances electrical performance by providing a highly planar structure with improved uniformity and reduced backend processing temperatures, enabling better device characteristics and manufacturing efficiency.
Implementation Method 1
chemical mechanical planarization (CMP) techniques to achieve a planar surface and ensure uniformity
Data Source
AI summary
A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches with a shield dielectric; using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon; forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches; lining upper sidewalls of the active gate trenches with a gate dielectric; and forming a gate electrode over the IPD in an upper portion of the active gate trenches.