Shielded Gate Trench Structure for Uniform Oxide Insulation
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Solution Overview
Problem
The shielded gate semiconductor device structure faces challenges due to the uneven thickness of the oxide layer in trenches, leading to potential gate-source short circuits and yield reliability issues, as the deeper trenches result in thinner oxide layers and crystal orientation differences, causing pits and residue of gate polycrystalline silicon in the source lead-out region.
Innovation Solution
A method involving sequential formation and removal of multiple oxide layers and polycrystalline silicon layers, with specific etching steps to ensure uniformity and complete removal of gate polycrystalline silicon from the source lead-out region, including forming a second oxide layer by chemical vapor deposition and a first oxide layer by thermal growth, followed by selective etching and deposition processes to achieve a stable oxide layer structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep trenches are etched to reduce parasitic capacitance, then the parasitic capacitance is reduced, but the oxide layer thickness becomes uneven and thinner at the bottom
Solution Approach 1:
The patent segments the oxide layer formation into two distinct parts: a first oxide layer grown by thermal oxidation and a second oxide layer deposited by CVD. This segmentation allows each layer to serve different functions - the first layer provides initial coverage while the second layer ensures uniform thickness throughout the deep trench, resolving the thickness uniformity issue caused by deep etching.
Solution Approach 2:
The patent transitions from a single-layer oxide structure to a multi-layer oxide structure, adding the dimension of layer stacking. By forming the first oxide layer at the bottom followed by the second oxide layer on top, the solution addresses the thickness variation problem by creating a composite structure where each layer compensates for the limitations of the other.
2Reliability
If thick oxide layers are formed to ensure adequate insulation, then insulation is improved, but pits are produced on trench sidewalls and gate polycrystalline silicon residue occurs
Solution Approach 1:
The patent applies local quality by forming the first oxide layer specifically at the bottom of the trench through thermal oxidation, providing localized insulation where it is most needed. The second oxide layer is then deposited to cover the entire trench structure, ensuring uniform insulation while maintaining sidewall integrity. This localized approach prevents the formation of pits and silicon residue.
3Manufacturing precision
If multiple oxide layers and etching steps are added to ensure uniform oxide thickness, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent employs preliminary action by first forming the deep trenches and then immediately growing the first oxide layer at the trench bottom through thermal oxidation before any other processing. This preliminary oxide layer formation ensures that the foundation for uniform insulation is established early, preventing subsequent manufacturing issues and reducing the need for additional corrective process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the complete removal of gate polycrystalline silicon from the source lead-out region, preventing gate-source short circuits and improving yield and reliability by maintaining a consistent oxide layer thickness and structure.
Implementation Method 1
forming a second oxide layer and a first oxide layer sequentially from outside to inside on inner surfaces of both a cell trench and a source lead-out region trench
Implementation Method 2
forming a second oxide layer and a first oxide layer sequentially from outside to inside on inner surfaces of both a cell trench and a source lead-out region trench
Data Source
AI summary
A method for preparing a shielded gate semiconductor device structure, and a shielded gate semiconductor device structure. The following steps are added in between source polycrystalline silicon deposition and gate polycrystalline silicon oxidation: removing, by etching, a first oxide layer and a second oxide layer that are in a middle upper space of a cell trench and on the surface of a semiconductor material layer, and a portion of the semiconductor material layer between trenches; removing, by etching, the gate polycrystalline silicon until a thickness of remaining gate polycrystalline silicon in the source lead-out region trench reaches a preset thickness; and selectively removing, by etching, remaining gate polycrystalline silicon in the source lead-out region trench until no gate polycrystalline silicon remains in the source lead-out region trench, and then removing the photoresist.