Shielded Gate Step Structure for Low-Capacitance Power Semiconductors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power semiconductor devices face challenges in increasing breakdown voltage and reducing on-resistance while maintaining low gate-to-drain capacitance as they are micronized, which affects their response speed and switching power loss.
Innovation Solution
The semiconductor device incorporates a shielded gate structure with a bottom gate having a step structure of electrodes, where the width of the top gate is smaller than the closest electrode, and a control gate separated by insulating layers, to enhance breakdown voltage and reduce on-resistance, thereby maintaining low gate-to-drain capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of power semiconductor devices is reduced (micronization), then device integration and compactness are improved, but breakdown voltage decreases and on-resistance increases
Solution Approach 1:
The gate structure is segmented into a control gate and a shielded gate (bottom gate), with the shielded gate further divided into multiple electrodes of different widths. This segmentation allows independent optimization of each segment's function, enabling the device to achieve high breakdown voltage through the shielded gate's field distribution while maintaining compact size through the control gate's precise positioning.
Solution Approach 2:
The shielded gate electrodes are designed with different widths at different locations (local areas), creating non-uniform charge distribution that optimizes the electric field locally. The wider electrodes are positioned to enhance field distribution in critical regions, improving breakdown voltage locally without requiring overall device enlargement.
2Volume of moving object
If the size of power semiconductor devices is reduced (micronization), then device integration is improved, but on-resistance increases
Solution Approach 1:
The segmented shielded gate structure with multiple electrodes creates optimized charge distribution that reduces the depletion region width, thereby reducing on-resistance. The control gate's independent positioning allows precise control of the channel formation, ensuring low resistance paths are maintained even in miniaturized devices.
3Strength
If shielded gate structure is used, then breakdown voltage is improved and on-resistance is reduced, but gate-to-drain capacitance increases
Solution Approach 1:
The shielded gate electrodes are designed with different widths at different locations, creating non-uniform charge distribution that optimizes the electric field locally. The wider electrodes are positioned to enhance field distribution in critical regions, improving breakdown voltage locally without requiring overall device enlargement.
Solution Approach 2:
The shielded gate electrodes are designed with asymmetric width distribution, where electrodes closer to the drain have different widths than those near the source. This asymmetric design optimizes the electric field distribution to reduce capacitance coupling between gate and drain, while still providing the breakdown voltage enhancement benefits of a shielded gate structure.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate and a gate structure. The gate structure is disposed in the substrate and includes a shielded gate, a control gate, and a plurality of insulating layers. The shielded gate includes a bottom gate and a top gate. The bottom gate includes a step structure consisting of a plurality of electrodes. A width of the electrode is smaller as the electrode is farther away from the top gate, and a width of the top gate is smaller than a width of the electrode closest to the top gate. The control gate is disposed on the shielded gate. A first insulating layer is disposed between the shielded gate and the substrate. A second insulating layer is disposed on the shielded gate. A third insulating layer is disposed between the control gate and the substrate.