Shielded Gate Trench FET IED Layer Oxidation
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Solution Overview
Problem
Conventional shielded gate trench FETs face challenges with high on-resistance (RDSon), limited blocking voltage, and gate charges due to misalignment tolerances and interface trap charges in the inter-electrode dielectric (IED) layer, which affect the device's performance and reliability.
Innovation Solution
The method involves forming a trench in a semiconductor region with a dielectric layer lining the sidewalls and bottom, followed by a shield electrode and an IED layer formed using steam ambient oxidation and dry ambient oxidation, with optional inert anneal or high-density plasma processes to improve the IED layer quality and reduce misalignment issues, allowing for self-aligned source and heavy body regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the IED dielectric layer is made thicker to support required voltage, then breakdown voltage is improved, but alignment difficulty increases and manufacturing complexity worsens
Solution Approach 1:
The patent changes the physical and chemical parameters of the IED layer by using steam ambient oxidation followed by dry ambient oxidation at different temperatures. This creates a multi-layer dielectric structure with optimized thickness distribution that achieves required breakdown voltage while maintaining manufacturability and alignment precision.
Solution Approach 2:
The patent creates a composite dielectric structure consisting of multiple oxidation layers with different properties. The steam oxidation layer provides one set of characteristics while the dry oxidation layer provides another, combining their benefits to achieve both high breakdown voltage and good alignment characteristics.
2Loss of energy
If the cell pitch is reduced to increase trench density, then on-resistance is improved, but misalignment tolerance decreases and manufacturing precision worsens
Solution Approach 1:
The patent changes the oxidation parameters (steam ambient followed by dry ambient at higher temperature) to create an IED layer with optimized electrical and physical properties. This allows reduced cell pitch and lower on-resistance while maintaining sufficient misalignment tolerance through the improved dielectric characteristics.
3Reliability
If interface trap charges and oxide trap charges are reduced in the IED layer, then device reliability is improved, but manufacturing complexity increases due to additional process steps
Solution Approach 1:
The patent uses steam ambient oxidation followed by dry ambient oxidation at higher temperature to fundamentally change the dielectric formation process. This parameter change reduces interface trap charges and oxide trap charges inherently through the oxidation mechanism, improving reliability without requiring additional complex process steps.
Solution Approach 2:
The patent employs steam ambient oxidation which provides accelerated oxidation compared to conventional methods. This strong oxidation process creates a higher quality dielectric with fewer traps and defects, improving device reliability while maintaining process efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces on-resistance, enhances blocking voltage, and improves the safe operating area and unclamped inductive switching capability of the power FETs, leading to lower on-state and switching losses and higher power conversion efficiencies.
Implementation Method 1
An inter-electrode dielectric (IED) is formed in the trench over the shield electrode by carrying out a steam ambient oxidation
Implementation Method 2
carrying out a dry ambient oxidation
Data Source
AI summary
In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.