Shielded Gate Trench FET Multiple Channel Segmentation

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Solution Overview

Problem

Existing shielded gate trench FETs face challenges in improving electrical characteristics such as breakdown voltage and on-resistance without compromising other performance metrics, as most techniques either adversely impact other characteristics or require significant changes to the process technology.

Innovation Solution

The implementation of shielded gate trench FETs with multiple channels along each trench sidewall, achieved by embedding additional well regions in the drift region next to the shield electrode, which allows for the formation of multiple current paths and channels, thereby enhancing breakdown voltage, reducing on-resistance, and improving unclamped inductive switching and snapback characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional well regions are embedded in the drift region next to the shield electrode to form multiple channels, then breakdown voltage is improved and on-resistance is reduced, but device complexity increases

Engineering Contradiction:
Improvebreakdown voltageVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The drift region is segmented into multiple channels by embedding additional well regions (first well region and second well region) between the trenches. These well regions divide the drift region into separate current paths, allowing multiple channels to form between the source and drain regions. This segmentation increases breakdown voltage by distributing the electric field across multiple channels and reduces on-resistance by providing parallel current paths.

Inventive Principle:
Principle #1Segmentation

2Reliability

If multiple channels are formed along each trench sidewall, then on-resistance is reduced, but manufacturing precision requirements increase

Engineering Contradiction:
Improveon-resistanceVSAvoidmanufacturing precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The formation of multiple channels is merged with the existing trench fabrication process. The first and second well regions are embedded in the drift region using the same trench structure and shielding electrode approach that is already established in conventional FET manufacturing. This integration allows multiple channels to be formed without requiring entirely new manufacturing processes, thereby reducing the increase in manufacturing precision requirements.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If shield electrode is added under gate electrode, then breakdown voltage is improved, but gate charge increases

Engineering Contradiction:
Improvebreakdown voltageVSAvoidgate charge
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The shield electrode is positioned in the vertical dimension below the gate electrode, creating a three-dimensional electrode structure. This vertical arrangement allows the shield electrode to extend into the drift region and form multiple channels, increasing breakdown voltage without requiring additional lateral space. The multi-channel structure provides parallel current paths that reduce the overall gate charge by distributing the capacitive load across multiple channels.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9224853B2Shielded gate trench FET with multiple channels
Publication Date: 2015.12.29 SEMICON COMPONENTS IND LLC
  • US9224853B2 patent drawing
  • US9224853B2 patent drawing
  • US9224853B2 patent drawing

AI summary

In one embodiment, an apparatus can include a trench extending into a semiconductor region of a first conductivity type, an electrode disposed in the trench, and a source region of the first conductivity type abutting a sidewall of the trench. The apparatus can include a first well region of a second conductivity type disposed in the semiconductor region below the source region and abutting the sidewall of the trench lateral to the electrode where the second conductivity type is opposite the first conductivity type. The apparatus can also include a second well region of the second conductivity type disposed in the semiconductor region and abutting the sidewall of the trench, and a third well region of the first conductivity type disposed between the first well region and the second well region.