Shielded Gate Trench FET Shield-Gate Connection
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Solution Overview
Problem
The existing process for forming shielded gate trench FETs requires a high-quality inter-electrode dielectric (IED) to support the potential difference between the shield and gate electrodes, which complicates the manufacturing process and is not always reliable.
Innovation Solution
The shield and gate electrodes are electrically connected through a second interconnect layer in a non-active region, eliminating the need for a high-quality IED by biasing the shield electrode to the same potential as the gate electrode, thereby reducing the on-resistance while simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a high-quality inter-electrode dielectric (IED) is used to support the potential difference between shield and gate electrodes, then the breakdown voltage is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent extracts and removes the IED layer from the device structure, eliminating the need for high-quality dielectric material and complex formation processes. The shield electrode is directly connected to the gate electrode through a conductive path in the non-active region, removing the dielectric barrier that caused manufacturing complexity while maintaining electrical isolation where needed.
Solution Approach 2:
The patent creates an equipotential connection between the shield electrode and gate electrode by directly connecting them in the non-active region. This eliminates the potential difference that would otherwise require a high-quality IED to support, thereby reducing breakdown voltage requirements and simplifying manufacturing while maintaining device performance.
2Reliability
If a high-quality inter-electrode dielectric (IED) is used to support the potential difference between shield and gate electrodes, then the electrical reliability is improved, but the manufacturing process becomes more complicated
Solution Approach 1:
The IED layer is completely removed from the structure. The shield and gate electrodes are directly connected through a conductive path formed in the non-active region, eliminating the need for dielectric deposition, patterning, and etching processes that complicate manufacturing while maintaining electrical reliability through direct metal-to-metal contact.
Solution Approach 2:
Instead of isolating the shield and gate electrodes with a dielectric layer as in conventional designs, the patent inverts the approach by directly connecting them through a conductive path. This inversion eliminates the need for complex dielectric processing while achieving the desired electrical characteristics through alternative means.
3Reliability
If the shield and gate electrodes are electrically connected together in the non-active region, then the on-resistance is reduced, but the device structure becomes more complex
Solution Approach 1:
The connection between shield and gate electrodes is achieved by extending them into the non-active region laterally, utilizing the horizontal dimension rather than adding vertical complexity. This lateral extension allows direct electrical connection without adding layers or complex three-dimensional structures, reducing on-resistance while maintaining structural simplicity.
Data Source
AI summary
A field effect transistor (FET) includes a plurality of trenches extending into a semiconductor region. Each trench includes a gate electrode and a shield electrode with an inter-electrode dielectric therebetween. A body region extends between each pair of adjacent trenches, and source regions extend in each body region adjacent to the trenches. A first interconnect layer contacts the source and body regions. The plurality of trenches extend in an active region of the FET, and the shield electrode and gate electrode extend out of each trench and into a non-active region of the FET where the shield electrodes and gate electrodes are electrically connected together by a second interconnect layer. The electrical connection between the shield and gate electrodes is made through periodic contact openings formed in a gate runner region of the non-active region.