Shielded Gate Trench MOS Source Pickup Layout
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Solution Overview
Problem
Existing fabrication techniques for shielded gate trench MOSFETs are complex and expensive, often requiring multiple masks, leading to issues such as low breakdown voltage due to body implant blocking and non-uniform trench widths, as well as void formation in high aspect ratio trenches.
Innovation Solution
The method involves relocating source poly pickup contacts outside the termination trenches and using a dep-etch-dep technique for filling high aspect ratio trenches to avoid voids, reducing the number of masks required and improving trench uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source poly pickup contacts are located within termination trenches, then device performance is maintained, but body implant blocking occurs causing low breakdown voltage
Solution Approach 1:
The source poly pickup contacts are extracted from the termination trenches and relocated to regions outside the termination trenches. This separation eliminates the body implant blocking effect that occurs when source poly is positioned within termination trenches, thereby resolving the harmful factor while maintaining device functionality.
2Ease of manufacture
If conventional fabrication techniques are used, then shielded gate trench MOSFETs can be manufactured, but the process is complex and expensive requiring 6 or more masks
Solution Approach 1:
The fabrication process merges multiple steps into fewer operations. Specifically, the method combines the formation of termination trenches and source poly pickup contacts into a single etching step using a single mask, and combines polysilicon deposition for both gate and source regions into unified steps. This integration reduces the total mask count from 6 or more to just 4 masks, significantly simplifying the manufacturing process.
Solution Approach 2:
The termination trenches serve multiple functions: they provide electrical isolation, define device boundaries, and act as etch stop regions. Additionally, the single polysilicon deposition process simultaneously forms both gate polysilicon and source polysilicon regions, reducing process steps and mask requirements through multi-functionality.
3Manufacturing precision
If high aspect ratio trenches are filled with polysilicon, then source poly pickup contacts are formed, but voids form in the trenches
Solution Approach 1:
The trenches are partially filled with polysilicon in a preliminary step, then etched back to remove excess material and prevent void formation. This preliminary filling followed by etch-back creates a controlled deposition process that eliminates the voiding problem inherent in direct high-aspect-ratio trench filling.
Solution Approach 2:
The polysilicon filling process is segmented into multiple stages: initial partial filling, etch-back to remove excess, and subsequent completion of the fill. This segmentation of the deposition process allows control over void formation by breaking the single filling operation into manageable steps with intermediate removal of problematic material.
4Manufacturing precision
If multiple masks are used for fabrication, then precise device features can be created, but manufacturing cost increases
Solution Approach 1:
The fabrication process merges multiple patterning operations into fewer mask steps. The single mask used for etching termination trenches and source poly pickup contacts simultaneously defines both features, eliminating the need for separate masks and reducing manufacturing cost while maintaining the required precision for each feature.
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.