Shielded Gate Trench MOSFET Self-Aligned Fabrication
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Solution Overview
Problem
Advanced trench MOSFET devices face challenges with increasing thermal resistance and robustness, particularly in smaller die sizes, due to issues like mask misalignment causing p body to source shorting resistance and inadequate avalanche breakdown localization.
Innovation Solution
The method involves forming shielded gate trench MOSFET devices with specific trench structures and processes, including the growth of shield oxide layers, doped poly silicon layers, and inter poly dielectric layers to minimize thickness variations and enhance robustness, thereby reducing thermal resistance and improving current handling capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If die size is reduced to decrease resistance per square area, then resistance decreases, but thermal resistance increases
Solution Approach 1:
The patent divides the semiconductor device into multiple discrete cells arranged in an array. Each cell contains its own trench structure with gate, source, and drain regions. This segmentation allows current to be distributed across multiple parallel paths, reducing overall resistance while maintaining a compact die size. The segmented structure also improves thermal management by distributing heat generation across multiple smaller regions rather than concentrating it in a single large area.
2Manufacturing precision
If die size is reduced, then resistance per square area decreases, but robustness against high current density deteriorates
Solution Approach 1:
The patent implements different structural characteristics in different regions of the device. The trench structures include selectively positioned p-body regions that create localized junctions with specific breakdown characteristics. The gate trench depth, width, and doping profiles are optimized locally to ensure avalanche breakdown occurs in the active cell regions rather than in termination areas. This local optimization ensures each region contributes appropriately to overall device robustness under high current density conditions.
3Manufacturing precision
If mask alignment is improved to reduce p body to source shorting resistance, then shorting resistance decreases, but device complexity increases
Solution Approach 1:
The patent employs self-aligned fabrication techniques where the p-body contact trenches are positioned relative to the gate trenches through the trench structure itself rather than requiring separate mask alignment steps. The alternating arrangement of gate and contact trenches, combined with selective etching and doping processes, allows the structure to define its own alignment automatically. This self-alignment mechanism reduces dependence on precise mask registration while maintaining low shorting resistance between p-body and source regions.
4Reliability
If avalanche breakdown is localized in active device cells, then device robustness improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates preliminary structural features during fabrication that pre-determine where avalanche breakdown will occur. The trench structures are formed with specific depth profiles, doping concentrations, and geometric dimensions that create predetermined electric field distribution patterns. By carefully designing the trench depth, width, and p-body region positioning during the fabrication process, the breakdown characteristics are established in advance, ensuring avalanche occurs in the desired active cell regions rather than requiring post-fabrication adjustment or extremely tight process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced drain to source resistance and gate to drain capacitance variations, improved high temperature gate bias reliability, and enhanced robustness against high current density and inductive operations.
Implementation Method 1
growing a shield oxide layer including silicon oxide on side walls and a bottom wall of each gate trench
Implementation Method 2
growing a gate oxide layer on the trench side walls and exposed silicon surfaces
Data Source
AI summary
A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly silicon oxide (IPO) layer. The IPO layer can be formed by either depositing a silicon oxide layer or thermally growing a poly silicon oxide layer with minimal thickness variation. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.