Shielded Gate Trench MOSFET with Split Electrode
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Solution Overview
Problem
Conventional trench MOSFETs face challenges in scaling down to pitches less than 1 μm due to thick liner oxide requirements, leading to high gate-to-drain capacitance and unstable processes, which affect high-frequency switching performance.
Innovation Solution
The development of a shielded gate trench MOSFET with a shallow trench and thin oxide liner, along with a thin inter-poly oxide, reduces gate-to-drain capacitance and maintains low on-state resistance, even at small pitches, by using a T-shaped or split-gate electrode configuration and constant dopant concentration in the epitaxial layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional trench MOSFET structure with thick liner oxide is used, then breakdown voltage is maintained, but gate-to-drain capacitance increases and high-frequency switching performance deteriorates
Solution Approach 1:
The gate electrode is segmented into two parts: an upper gate electrode and a lower gate electrode (shield electrode), separated by an inter-poly oxide layer. This segmentation allows the upper gate to control the channel while the lower gate shields the electric field in the drift region, reducing gate-to-drain capacitance without compromising breakdown voltage
Solution Approach 2:
A thin inter-poly oxide layer is introduced as an intermediary between the upper and lower gate electrodes. This intermediary layer enables electrical isolation between the two gates while maintaining a compact structure that reduces the overall gate-to-drain capacitance compared to conventional single-gate designs
2Reliability
If trench gate is placed to form vertical channel to decrease on-resistance, then on-state resistance is reduced, but gate-to-drain capacitance increases
Solution Approach 1:
The gate structure is divided into upper and lower segments that can be independently controlled. The lower gate electrode extends into the drift region to provide shielding, while the upper gate electrode forms the control gate, allowing simultaneous optimization of on-resistance and gate-to-drain capacitance
Solution Approach 2:
Different regions of the gate structure have different functions: the upper gate electrode provides channel control with standard dimensions, while the lower gate electrode provides electric field shielding in the drift region. This local differentiation allows the structure to simultaneously achieve low on-resistance and reduced gate-to-drain capacitance
3Productivity
If scaling down to pitches less than 1 μm is attempted, then device density increases, but thick liner oxide requirements cause process instability
Solution Approach 1:
The oxide liner thickness is reduced from conventional thick dimensions to a thin dimension suitable for sub-1 μm pitches. This parameter change enables scaling to higher device densities while maintaining process stability, as the thin oxide liner is less susceptible to variability and defect formation at small dimensions
4Object-affected harmful factors
If shielded gate trench MOSFET structure is used, then gate-to-drain capacitance is reduced, but fabrication complexity increases
Solution Approach 1:
The formation of the upper and lower gate electrodes is merged with standard CMOS fabrication processes. The inter-poly oxide layer is formed using conventional oxide deposition and etching techniques, and the gate electrodes are patterned and filled in sequence using standard process steps, thereby reducing fabrication complexity compared to entirely new process methodologies
Data Source
AI summary
A shielded gate trench field effect transistor comprises an epitaxial layer above a substrate, a body region, a trench formed in the body region and epitaxial layer and one or more source regions formed in a top surface of the body region and adjacent a sidewall of the trench. A shield electrode is formed in a lower portion of the trench and a gate electrode is formed in an upper portion of the trench above the shield electrode. The shield electrode is insulated from the epitaxial layer by a first dielectric layer. The gate electrode is insulated from the epitaxial layer by the first dielectric layer and insulated from the shield electrode by a second dielectric layer. The first and second dielectric layer has a same thickness.