Shielded JFET Semiconductor Structure for Leakage Suppression
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Solution Overview
Problem
Drain-source leakage current becomes a significant issue in semiconductor components as the design depth of well regions becomes shallower, leading to increased power consumption.
Innovation Solution
Incorporation of shield regions with varying carrier concentrations between the junction gate field-effect transistor (JFET) region and well region, specifically using first and second shield regions with increasing carrier concentrations, to mitigate drain-source leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the design depth of well region is reduced to make semiconductor device smaller, then the size of semiconductor device is reduced, but drain-source leakage current increases
Solution Approach 1:
The patent introduces shield regions as intermediary structures between the well region and JFET region. These shield regions act as mediators to block the harmful leakage current while allowing the well region depth to be reduced for smaller device size. The shield regions with graded carrier concentrations create potential barriers that prevent carrier leakage without requiring deeper well regions.
Solution Approach 2:
The patent changes the carrier concentration parameter by creating shield regions with graded doping concentrations. The first shield region has a carrier concentration higher than the well region, and the second shield region has an even higher carrier concentration. This parameter gradient creates effective potential barriers that suppress leakage current while maintaining shallow well region depth.
2Loss of energy
If shield regions with graded carrier concentrations are added to reduce leakage current, then drain-source leakage current is reduced, but device structure becomes more complex
Solution Approach 1:
The patent divides the shielding function into multiple segments - the first shield region and the second shield region with different carrier concentrations. This segmentation allows each region to perform the leakage suppression function at different locations and with different doping levels, achieving effective leakage control while maintaining a systematic and organized structure.
Solution Approach 2:
The patent applies local quality by creating regions with different carrier concentrations at specific locations. The first shield region has a carrier concentration higher than the well region, while the second shield region has an even higher carrier concentration. This localized variation in doping quality allows effective leakage suppression at each critical interface without requiring uniform high doping throughout the entire device.
Data Source
AI summary
A semiconductor device includes a substrate, a drift region, a well region, a first shield region, a junction gate field-effect transistor (JFET) region, a source region and a gate structure. The first shield region is located in the drift region, in which a bottom surface of the first shield region is lower than a bottom surface of the well region and a carrier concentration of the first shield region is greater than a carrier concentration of the well region. The JFET region is located in the drift region, in which a bottom surface of the JFET region is lower than a bottom surface of the first shield region. A first portion of the first shield region is located between the well region and the JFET region. The source region is adjacent to the well region. The gate structure is located on the drift region.