Shielded JFET Structure for Lower Miller Capacitance

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Solution Overview

Problem

Semiconductor devices with junction-type field effect transistors face challenges in reducing switching loss due to high Miller capacitance ratios, which can lead to increased surge current concentration and threshold voltage magnitude.

Innovation Solution

Incorporating a shield layer between the gate and drift layers, maintained at a potential different from the gate layer, with a depth ratio of the gate layer to the body layer equal to or smaller than 0.45, reduces the Miller capacitance ratio and suppresses the increase in threshold voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a junction-type field effect transistor is used with conventional structure, then the device can operate with basic functionality, but the Miller capacitance ratio is high leading to increased switching loss

Engineering Contradiction:
Improveswitching lossVSAvoiddevice structure
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The device is segmented into multiple functional layers including drift layer, channel layer, source layer, gate layer, body layer, and shield layer. This segmentation allows each layer to perform its specific function optimally, with the shield layer specifically designed to reduce Miller capacitance and the body layer to control surge current, thereby reducing overall switching loss without excessive complexity increase

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A shield layer is introduced as an intermediary element between the gate layer and drift layer. This shield layer acts as a mediator to reduce the Miller capacitance ratio by controlling the electric field distribution, thereby reducing switching loss while maintaining manageable device structure

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If the gate layer is positioned deeper in the channel layer, then the control over channel is improved, but the threshold voltage magnitude increases

Engineering Contradiction:
Improvechannel controlVSAvoidthreshold voltage magnitude
Core Design Contradiction:
Ease of operationVSObject-generated harmful factors

Solution Approach 1:

The depth ratio of the gate layer to the body layer is optimized to be equal to or smaller than 0.45. This parameter change allows the gate layer to be positioned deep enough to provide good channel control while preventing the threshold voltage magnitude from becoming excessively large, achieving a balanced operating point

Inventive Principle:
Principle #35Parameter changes

3Power

If surge current is allowed to flow freely, then the device can handle high current demands, but the surge current concentrates on the gate layer causing damage

Engineering Contradiction:
Improvecurrent handling capabilityVSAvoidgate layer protection
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

A body layer is introduced as an intermediary structure to intercept and divert surge current away from the gate layer. This body layer acts as a protective mediator that handles the surge current, preventing it from concentrating on the gate layer and causing damage, while still allowing the device to handle high current demands through the drain layer

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11923461B2Semiconductor device
Publication Date: 2024.03.05 DENSO CORP
  • US11923461B2 patent drawing
  • US11923461B2 patent drawing

AI summary

A semiconductor device includes a drift layer, a channel layer, a source layer being the first conductivity type, a gate layer, a body layer, a shield layer and a drain layer. The channel is disposed on the drift layer. The source layer is disposed on a surface layer portion of the channel layer. The gate layer is arranged to be deeper than the source layer. The body layer is arranged to be deeper than the source layer. The shield layer is disposed at a portion of the channel layer between the gate layer and the drift layer. The shield layer is maintained at a potential different from a potential of the gate layer. The drain layer is disposed at a side opposite to the channel layer. A depth ratio of a depth of the gate layer to a depth of the body layer is equal to or larger than 0.45.