Shielded Voltage-Level Shifter for Low-Stress Low-Power Switching
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Solution Overview
Problem
Negative level shifters face a dilemma between power consumption and voltage stress risk, especially in low-voltage applications where the large voltage difference between stages can lead to increased switching delay and dynamic power consumption, necessitating a solution that balances these factors for efficient and low-power operation.
Innovation Solution
The design incorporates an input stage circuit with a comparator, current mirror, and shielding circuits to reduce voltage stress, coupled with a push-pull stage circuit that generates output signals with controlled voltage swings, utilizing transistors with specific voltage configurations to manage stress and optimize power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a second stage circuit is added to convert voltages between stages, then voltage stress risk is reduced, but power consumption increases
Solution Approach 1:
The patent introduces a voltage conversion circuit as an intermediary stage between the first and third stage circuits. This intermediate circuit converts the first intermediate signal from the first stage into a second intermediate signal with appropriate voltage levels for the third stage, thereby reducing voltage stress on individual components while maintaining power efficiency through optimized switching mechanisms.
Solution Approach 2:
The voltage conversion function is segmented into multiple stages: the first stage circuit generates initial intermediate signals, the voltage conversion circuit processes these into second intermediate signals with reduced voltage stress, and the third stage circuit produces final output signals. This segmentation allows each stage to operate within optimized voltage ranges, reducing overall power consumption while managing voltage stress.
2Use of energy by moving object
If positive system voltage is lowered below 1.5V to reduce power consumption, then dynamic power consumption decreases, but switching delay increases due to serious contention between pull-up and pull-down transistors
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting the operating voltages at different stages of the circuit. The voltage conversion circuit transforms signals from the low-voltage first stage (below 1.5V) into appropriate voltage levels for the third stage, optimizing the balance between power consumption and switching speed by controlling voltage transitions and transistor switching timing.
Data Source
AI summary
The present invention provides a voltage level shifter architecture applicable for positive and negative voltage shifting, in which a shielding circuit is configured to relax the voltage stress of the transistors in the input stage circuit, and a switching circuit is configured to avoid current leakage. In addition, designing the power domain(s) of the n-well P-type transistors in the voltage-level shifter makes the voltage-level shifter area-efficient and power-efficient or design-flexible and application-adaptive.