Shielded MOM Capacitor with Segmented Middle Plate

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Solution Overview

Problem

There is a need for a shielded metal-oxide-metal (MOM) capacitor that meets the requirements of low RC parasitic capacitance and a unit capacitance of at least 1fF for 10-bits successive approximation register analog-to-digital converters (SAR ADCs) in RF and mixed-signal applications.

Innovation Solution

A shielded MOM capacitor is designed with a three-layer or five-layer stack structure, featuring lower and upper shielding plates, a middle plate, and intermediate shielding plates, which provide a low RC parasitic configuration and a unit capacitance of at least 1fF, utilizing insulation materials like extreme low k (ELK) and fabricated using existing metal layers in the CMOS process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a conventional MOM capacitor structure is used, then the device complexity is low, but the RC parasitic capacitance is high

Engineering Contradiction:
ImproveRC parasitic capacitanceVSAvoidcapacitor structure complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The capacitor structure is segmented into multiple functional layers: signal plates (for capacitance function), shielding plates (for parasitic reduction), and intermediate structures. This segmentation allows each component to perform its specific function independently, achieving low RC parasitic capacitance through dedicated shielding layers while maintaining the capacitance function through signal plates.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Intermediate structures (such as intermediate shielding plates or dielectric layers) are introduced between the signal plates and external environment to mediate the electrical interaction. These intermediary elements act as buffers that reduce parasitic coupling while maintaining the primary capacitance function, effectively lowering RC parasitic capacitance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If the capacitor unit capacitance is increased to meet 10-bits ADC requirements, then the capacitance value increases, but the area occupied increases

Engineering Contradiction:
Improveunit capacitanceVSAvoidcapacitor area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The capacitor design transitions from a planar two-dimensional layout to a three-dimensional stacked structure with multiple layers in the vertical dimension. By stacking signal plates and shielding plates vertically, the capacitance increases through additional capacitive elements in series/parallel combinations, while the footprint area remains constrained to the substrate plane, achieving high unit capacitance with minimal area occupation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The capacitor employs composite material structures combining different dielectric materials with varying permittivity values in different layers. High-k dielectric materials are strategically positioned to maximize capacitance density in specific regions, while low-k materials are used in other areas to reduce parasitic effects. This composite approach enables achieving the required 1fF unit capacitance within limited area by optimizing the electrical properties of each material layer.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The shielded MOM capacitor effectively reduces RC parasitic capacitance and achieves a unit capacitance of at least 1fF, making it suitable for 10-bits SAR ADCs, enhancing performance in RF and mixed-signal applications.

Implementation Method 1

utilizing insulation materials like extreme low k (ELK)

Methodology Applied
Scientific EffectDielectric property: Dielectric

Implementation Method 2

A shielded metal-oxide-metal (MOM) capacitor... achieves a unit capacitance of at least 1fF

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentEP3493284B1Shielded MOM capacitor
Publication Date: 2023.05.03 MEDIATEK INC
  • EP3493284B1 patent drawingFigure 1
  • EP3493284B1 patent drawingFigure 2
  • EP3493284B1 patent drawingFigure 3

AI summary

A shielded metal-oxide-metal, MOM, capacitor includes a substrate (10), a lower shielding plate (20) disposed on the substrate (10) and in parallel with a major surface of the substrate (10), an upper shielding plate (40) situated above the lower shielding plate (20) and in parallel with the lower shielding plate (20), and a middle plate (30) sandwiched between the lower shielding plate (20) and the upper shielding plate (40). The middle plate (30) includes two parallel first connecting bars (301a, 301b) extending along a first direction, a plurality of first fingers (302) extending between the two parallel first connecting bars (301a, 301b) along a second direction, and an electrode strip (304) spaced apart from and surrounded by the two parallel first connecting bars (301a, 301b) and the first fingers (302).