3D Die-Stacked Microelectronic Assembly With Shielded Pillar Interconnects
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Solution Overview
Problem
Conventional microelectronic assemblies face challenges in efficiently communicating large numbers of signals between IC dies due to the small size of dies, thermal constraints, and power delivery limitations, leading to reduced bandwidth, increased latency, and larger package sizes.
Innovation Solution
The proposed microelectronic assembly includes a package substrate with embedded dies and a shield structure that surrounds conductive pillars, allowing for direct and efficient interconnects between dies and the substrate, reducing signal crosstalk, and enhancing power delivery while minimizing package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional substrates are used to couple IC dies, then mechanical stability is achieved, but interconnect pitch is constrained by manufacturing, materials, thermal considerations, and signal performance
Solution Approach 1:
The patent transitions from planar interconnect routing on conventional substrates to three-dimensional vertical interconnects using conductive pillars that extend through multiple die layers. This dimensional change enables finer interconnect pitch by utilizing the vertical dimension for signal routing, thereby overcoming the manufacturing and material constraints that limit two-dimensional substrate routing capabilities.
Solution Approach 2:
The patent embeds conductive pillars within dielectric layers and nests multiple functional layers (conductive, dielectric, shielding) within each other to create a compact multi-layer interconnect structure. This nesting approach allows high-density interconnect routing without increasing the lateral footprint, effectively overcoming substrate constraints while achieving fine interconnect pitch.
2Area of moving object
If die size is reduced to increase integration density, then more components fit in smaller packages, but thermal constraints and power delivery limitations increase
Solution Approach 1:
The patent replaces conventional lateral thermal spreading mechanisms with vertical thermal conduction pathways by integrating heat sink structures that extend downward through the substrate. This substitution enables efficient heat removal from miniaturized dies by creating direct thermal conduction paths to external heat sinks, overcoming thermal constraints associated with reduced die size.
Solution Approach 2:
The patent introduces intermediate thermal management structures, including thermally conductive dielectric materials and integrated heat sink pathways, that mediate between the miniaturized dies and external cooling systems. These intermediary structures enable effective thermal management in high-density configurations where direct die-to-heat-sink coupling is not feasible.
3Productivity
If conventional interconnect methods are used, then signal transmission is achieved, but bandwidth is reduced and latency is increased
Solution Approach 1:
The patent utilizes vertical three-dimensional interconnect pathways instead of lateral routing to create shorter and more direct signal transmission paths between dies. This dimensional change reduces signal path length and eliminates unnecessary routing detours, thereby decreasing latency and improving bandwidth for high-speed signal transmission.
Solution Approach 2:
The patent segments the interconnect system into dedicated functional layers, including separate signal, power, and ground pathways, as well as shielded and unshielded interconnect regions. This segmentation enables optimized signal routing with reduced crosstalk and interference, improving signal transmission efficiency and reducing latency.
4Volume of moving object
If package size is reduced for portable applications, then device portability is improved, but power delivery and signal performance deteriorate
Solution Approach 1:
The patent employs vertical power delivery pathways through conductive pillars and integrated power distribution networks that extend through multiple die layers. This three-dimensional power delivery architecture enables efficient power distribution in compact packages by utilizing the vertical dimension for current flow, maintaining power delivery capability while reducing lateral package dimensions.
Solution Approach 2:
The patent utilizes composite material structures, including conductive pillars with specialized materials, thermally conductive dielectric composites, and multi-layer material stacks with optimized electrical and thermal properties. These composite materials enable simultaneous achievement of compact package size and effective power delivery by providing materials with tailored electrical, thermal, and mechanical characteristics.
Data Source
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a first die, having opposing first and second surfaces, in a first dielectric layer, wherein the first dielectric layer is between a second dielectric layer and the surface of the package substrate, and the first surface of the first die is coupled to the surface of the package substrate; a second die, having opposing first and second surfaces, in the second dielectric layer, and wherein the second dielectric layer is between the first dielectric layer and a third dielectric layer; a third die, having opposing first and second surfaces, in the third dielectric layer, wherein the first surface of the third die is coupled to the surface of the package substrate by a conductive pillar; and a conductive, radio frequency shield structure surrounding the conductive pillar.