Shielded Pixel Circuit Layout for Under-Display Transmission Areas
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Solution Overview
Problem
Current display devices face challenges in reducing power consumption and maintaining high resolution while integrating electronic components that receive or transmit light, which can affect display quality due to external light interference.
Innovation Solution
The display device incorporates a layered structure with silicon and oxide semiconductor thin-film transistors, a bottom shielding layer, and a light shielding portion to protect pixel circuits from external light, allowing for efficient power use and expanded display areas even beneath light-emitting elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If electronic components are integrated beneath light-emitting elements to expand display area, then display area is increased, but external light interference affects pixel circuits causing display quality degradation
Solution Approach 1:
A bottom shielding layer is introduced as an intermediary component between the substrate and the pixel circuits to block external light from reaching and interfering with the pixel circuits, while still allowing the display area to be expanded beneath light-emitting elements
Solution Approach 2:
The shielding function is implemented in the vertical dimension (bottom layer) rather than occupying horizontal display space, allowing the display area to expand in the planar dimension while protection is provided in the vertical dimension
2Use of energy by moving object
If oxide semiconductor thin-film transistors are used in pixel circuits, then power consumption is reduced, but transistor performance and stability may be compromised
Solution Approach 1:
The pixel circuit employs a composite transistor structure combining oxide semiconductor and silicon semiconductor materials, where the oxide semiconductor layer provides low power consumption characteristics while the silicon semiconductor layer enhances transistor performance and stability
Solution Approach 2:
Different semiconductor materials are used in different regions of the transistor structure - oxide semiconductor in the channel region for low power consumption and silicon semiconductor in other regions for enhanced performance and stability
3Measurement precision
If display devices are miniaturized with higher integration, then resolution is improved, but power consumption increases
Solution Approach 1:
The transistor structure parameters are optimized by using thin-film semiconductor layers with specific thicknesses and material compositions that enable high integration for improved resolution while maintaining low power consumption characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces power consumption, enhances display quality by shielding pixel circuits from external light, and enables image display in areas with integrated electronic components, improving overall performance and reliability.
Implementation Method 1
a bottom shielding layer below the second semiconductor layer and overlapping at least a portion of the second semiconductor layer on a plane
Data Source
AI summary
An embodiment of a display device includes: a first display area; a second display area including a transmission area; a third display area between the first display area and the second display area; and a plurality of pixel circuits in the third display area and electrically connected to the plurality of third light-emitting elements, respectively. Each of the plurality of pixel circuits includes: a first thin-film transistor including a first semiconductor layer and a first gate electrode overlapping at least a portion of the first semiconductor layer; a second thin-film transistor including a second semiconductor layer including a material different from that of the first semiconductor layer and a second gate electrode overlapping at least a portion of the second semiconductor layer; and a bottom shielding layer below the second semiconductor layer and overlapping at least a portion of the second semiconductor layer on a plane.