Shielded TSVs in Passive Interposers
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Solution Overview
Problem
The increasing density and higher frequencies in 3D integrated circuits using through silicon vias (TSVs) lead to signal coupling interference, which existing guard ring shielding methods cannot fully address, resulting in performance issues and increased costs due to additional shielding layers and routing areas.
Innovation Solution
A passive interposer with a shielded TSV configuration is implemented, utilizing a p-doped semiconductor substrate with heavily doped regions and interlayer dielectric, where shielding lines are formed between TSVs to reduce interference, eliminating the need for extra shielding layers and minimizing routing area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If guard rings are used to shield TSVs, then signal coupling interference is reduced, but additional shielding layers and routing area are required, increasing cost and limiting shielding path
Solution Approach 1:
The patent transitions from planar guard ring shielding to three-dimensional doped region shielding within the substrate. By creating p-doped regions that extend vertically through the substrate thickness, the shielding effect is achieved in the third dimension (depth), eliminating the need for additional lateral shielding layers and expanding the effective shielding path without increasing routing area.
Solution Approach 2:
The patent changes the electrical parameters of the substrate by introducing heavily doped p-type regions. By modifying the doping concentration and distribution within the substrate, the electrical properties are altered to provide shielding against signal coupling interference, replacing the need for separate shielding structures with intrinsic substrate modification.
2Quantity of substance
If TSVs are placed closer together to increase density, then circuit density is improved, but signal coupling interference between TSVs increases
Solution Approach 1:
The patent applies localized p-doped regions between specific TSVs rather than uniformly doping the entire substrate. This local quality modification creates electrical barriers precisely where needed between adjacent TSVs, providing targeted shielding that enables closer TSV placement without compromising signal integrity in shielded regions.
Solution Approach 2:
The patent introduces p-doped substrate regions as intermediary elements between adjacent TSVs. These doped regions act as electrical mediators or barriers that prevent direct electromagnetic coupling between TSVs, allowing higher density placement while maintaining signal integrity through the intermediary shielding structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively shields more TSVs, improving signal integrity and reducing costs by minimizing the need for additional shielding layers and routing area, while maintaining performance across various frequencies.
Implementation Method 1
doping a substrate with positive ions, and implanting positive ions in an upper portion of the substrate, such that the substrate has at least a p-doped portion and a heavily p-doped upper portion
Data Source
AI summary
A method of shielding through silicon vias (TSVs) in a passive interposer includes doping a substrate with positive ions, and implanting positive ions in an upper portion of the substrate, such that the substrate has at least a p-doped portion and a heavily p-doped upper portion. The method further includes forming an interlayer dielectric (ILD) above the heavily p-doped upper portion. The method further includes forming a plurality of through silicon vias (TSVs) through the ILD and the substrate, such that the passive interposer is configured to electrically couple at least one structure above and below the passive interposer. The method further includes forming, between pairs of TSVs of the plurality of TSVs, a plurality of shielding lines through the interlayer dielectric, the shielding lines configured to electrically couple the heavily p-doped upper portion of the substrate and at least one interconnect structure above the ILD.


