Shielded Superjunction VJFET Reducing Gate-Drain Capacitance
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Solution Overview
Problem
High-voltage VJFETs face challenges in reducing on-resistance and gate-drain capacitance (Cgd) while maintaining high switching speed and reliability, particularly when integrating a superjunction charge-balance technique that connects the p-column to the p-gate, leading to increased Cgd.
Innovation Solution
The implementation of a shielded superjunction JFET structure, where a buried shield is connected to the source electrode, reducing the effective Cgd by electrically linking the source electrode to the buried shield, thereby maintaining the buried shield at source electrode potential, and optimizing doping levels to achieve lower on-resistance and reduced Cgd.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the p-column is connected to the p-gate in a superjunction VJFET, then lower on-resistance is achieved, but gate-drain capacitance (Cgd) increases
Solution Approach 1:
The device is divided into distinct functional regions: a superjunction charge-balanced area for low on-resistance, a buried shield region for capacitance reduction, and a JFET area for current conduction. This segmentation allows each region to be optimized independently, resolving the contradiction between low on-resistance and low Cgd.
Solution Approach 2:
A buried shield consisting of alternating n-type and p-type columns is introduced as an intermediary structure between the superjunction area and the drain. This buried shield acts as a mediator that reduces the electric field and capacitance coupling between gate and drain, thereby reducing Cgd while preserving the low on-resistance特性 of the superjunction structure.
2Speed
If a buried shield is added to reduce Cgd, then switching speed improves, but device structure complexity increases
Solution Approach 1:
The buried shield structure merges multiple functions into a single region: it provides capacitance reduction, electric field shielding, and structural support. By combining these functions in one integrated structure rather than adding separate components, the increase in complexity is minimized while achieving the desired switching speed improvement.
Solution Approach 2:
The doping concentrations, widths, and depths of the buried shield regions are optimized as key parameters to achieve the desired Cgd reduction while maintaining manufacturability. By carefully controlling these parameters within practical ranges, the structure achieves performance goals without excessive complexity.
3Reliability
If superjunction charge-balance technique is used, then on-resistance decreases, but manufacturing complexity increases
Solution Approach 1:
The superjunction charge-balanced structure is formed in preliminary fabrication steps before final device assembly. The alternating n-type and p-type columns are pre-formed with controlled doping, and the charge balance is established during these initial processing stages, simplifying subsequent manufacturing steps.
Solution Approach 2:
The doping concentrations and geometric parameters of the superjunction columns are precisely controlled during fabrication to achieve charge balance. By optimizing these parameters upfront in the design stage, the manufacturing process achieves the desired low on-resistance with standard semiconductor fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves lower on-resistance and reduced Cgd, enhancing switching speed and reliability by effectively managing the electric field and current flow, making the devices more suitable for high-power applications.
Implementation Method 1
a superjunction charge balanced area that includes implanted regions of a first conductivity type and implanted regions of a second conductivity type
Implementation Method 2
an electrical link that may include at least one region of the second conductivity type of the link area electrically connected to and at least partially aligned with at least one region of the second conductivity type of the buried shield
Data Source
AI summary
The present disclosure describes structures and processes to produce high voltage JFETs in wide-bandgap materials, most particularly in Silicon Carbide. The present disclosure also provides for products produced by the methods of the present disclosure and for apparatuses used to perform the methods of the present disclosure.