Shielding Electrode Design for LCD Gate Signal Delay Reduction
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Solution Overview
Problem
Large-sized and high-resolution LCD panels experience increased gate signal delay due to higher resistance and parasitic capacitance in gate lines, which affects display quality and side viewing angles.
Innovation Solution
A display substrate design that includes a base substrate with a gate line, data line, pixel electrode, and shielding electrode, where the shielding electrode is formed from the same material as the pixel electrode and has a wider width to cover the gate line, with openings to reduce parasitic capacitance and signal delay, and a domain division pattern to enhance image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate line is made longer to accommodate larger display size, then the display area is increased, but the gate signal delay is increased due to higher resistance and parasitic capacitance
Solution Approach 1:
A shielding electrode is introduced as an intermediary component between the gate line and pixel electrode. This shielding electrode acts as a mediator to reduce parasitic capacitance between the gate line and pixel electrode, thereby decreasing gate signal delay without requiring changes to the gate line dimensions or material
2Loss of time
If the gate line material is changed to low-resistance metal to decrease resistance, then the gate signal delay is decreased, but the parasitic capacitance generation is suppressed
Solution Approach 1:
The shielding electrode serves as an intermediary that actively reduces parasitic capacitance between the gate line and pixel electrode. By introducing this intermediate component, the patent addresses parasitic capacitance reduction separately from resistance management, allowing low-resistance materials to be used without being constrained by parasitic capacitance issues
3Loss of time
If the gate line width is increased to reduce resistance, then the gate signal delay is decreased, but the parasitic capacitance between gate line and pixel electrode is increased
Solution Approach 1:
The shielding electrode is positioned between the gate line and pixel electrode to reduce parasitic capacitance. This intermediary structure allows the gate line width to be increased for lower resistance without proportionally increasing parasitic capacitance, as the shielding electrode mitigates the capacitive coupling
Solution Approach 2:
The shielding electrode is selectively positioned only in regions where parasitic capacitance reduction is most critical, specifically between the gate line and pixel electrode. This localized approach reduces parasitic capacitance where it most impacts gate signal delay, while allowing gate line width to be optimized for resistance reduction
Data Source
AI summary
A display substrate includes a base substrate, a gate line, a data line, a pixel electrode and a shielding electrode. The base substrate includes a plurality of unit pixel areas arranged in a matrix shape. The gate line extends between the unit pixel areas. The data line crosses the gate line. The data line extends between the unit pixel areas. The pixel electrode is disposed in the unit pixel area. The pixel electrode is electrically connected to an output electrode of a switching element electrically connected to the gate and data lines. The shielding electrode is disposed the gate and data lines. The shielding electrode has an opening an opening formed therein, the opening disposed above and extending along a direction of the gate line.