Shielding Electrode Reduces Parasitic Capacitance in Array Substrates
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Solution Overview
Problem
The parasitic capacitance between the data line and the common electrode layer in multidimensional electric field display panels is excessively large, leading to signal delay and a green image issue, which severely affects display quality.
Innovation Solution
Incorporating a shielding electrode layer grounded between the data line and the passivation layer, with an insulating barrier layer between the data line and the shielding electrode layer, to reduce parasitic capacitance by providing a pathway for excessive capacitance to be led out through grounding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a common electrode layer is formed covering the data line in a multidimensional electric field display panel, then the display mode can be implemented, but parasitic capacitance between the data line and common electrode layer becomes excessively large
Solution Approach 1:
A shielding electrode layer is introduced as an intermediary component between the data line and the common electrode layer. This shielding electrode is connected to ground potential and acts as a mediator to reduce the parasitic capacitance coupling between the data line and common electrode layer, thereby solving the capacitance problem while maintaining the multidimensional electric field display functionality
Solution Approach 2:
The harmful parasitic capacitance effect is extracted and isolated by introducing the shielding electrode layer grounded to potential. This separates the harmful capacitive coupling from the functional electric field between pixel electrode and common electrode, removing the detrimental effect while preserving the display function
2Device complexity
If parasitic capacitance between data line and common electrode layer is large, then the structure is simple, but signal delay occurs and display quality deteriorates
Solution Approach 1:
The shielding electrode layer serves as a grounded intermediary that reduces parasitic capacitance between the data line and common electrode layer. By minimizing the capacitive coupling, signal delay is reduced while the additional structural complexity is minimal, as the shielding electrode can be integrated into existing layer structures
3Ease of manufacture
If parasitic capacitance between data line and common electrode layer is large, then the manufacturing process follows conventional steps, but green image issue occurs and display quality is seriously affected
Solution Approach 1:
The shielding electrode layer is introduced as a grounded intermediary between the data line and common electrode layer to reduce parasitic capacitance. This prevents the green image artifact caused by excessive capacitance coupling, while the manufacturing process remains compatible with conventional thin-film deposition and patterning techniques
Solution Approach 2:
The shielding electrode layer is selectively positioned only in regions where parasitic capacitance reduction is needed, specifically between the data line and common electrode layer. This local application maintains ease of manufacture by targeting only the problematic areas rather than requiring comprehensive structural modifications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces parasitic capacitance, prevents signal delay, and improves display quality by eliminating the green image issue, enhancing the overall performance of the display device.
Implementation Method 1
a large parasitic capacitance can be generated between the common electrode layer and the data line
Data Source
AI summary
Provided are an array substrate and a manufacturing method therefor, and a display panel. The array substrate comprises: a base substrate; a data line and a passivation layer which are formed on the base substrate; a common electrode layer formed on the passivation layer; and a shielding electrode layer and a barrier layer which are formed on the base substrate, wherein the shielding electrode layer is arranged between the data line and the passivation layer, the barrier layer is arranged between the data line and the shielding electrode layer, the shielding electrode layer is grounded, and the barrier layer is made of a material with an insulation function.