Shielding Layer for Gate Clock Lines in Narrow Bezel Displays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional display devices with embedded gate driving circuits often experience abnormal operation, display abnormalities, output deviations of gate signals, load deviations between gate clock lines, and burnt defects due to the narrow bezel structure, which can lead to driving defects, image defects, and safety issues.
Innovation Solution
A display device with a reliability structure that includes a substrate divided into a display area and a non-display area, a gate driving circuit in the non-display area, gate clock lines outside the gate driving circuit, a passivation layer, a common electrode not overlapping with the gate clock lines, and a shielding layer overlapping with the gate clock lines to prevent parasitic capacitance and ensure reliable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If a gate driving circuit is embedded in a display panel to reduce bezel size, then the bezel size is reduced, but abnormal operation and display abnormalities occur
Solution Approach 1:
A shielding layer is introduced as an intermediary component between the gate clock lines and the common electrode. This shielding layer prevents parasitic capacitance formation by blocking the electromagnetic field interaction, thereby eliminating the abnormal operation while maintaining the narrow bezel structure.
Solution Approach 2:
The problematic overlapping configuration is separated by extracting the gate clock lines from the area where they would overlap with the common electrode. The shielding layer is positioned specifically under the gate clock lines to provide targeted protection without affecting the overall compact design.
2Reliability
If gate clock lines are disposed outside the gate driving circuit to reduce load deviation, then load deviation is reduced, but parasitic capacitance with common electrode increases
Solution Approach 1:
The shielding layer serves as a mediator that allows the gate clock lines to be disposed outside the gate driving circuit for load balancing, while simultaneously blocking the parasitic capacitance effect by preventing electromagnetic field coupling with the common electrode.
3Length of stationary object
If a narrow bezel structure is implemented with embedded gate driving circuit, then bezel size is reduced, but burnt defects and safety problems occur
Solution Approach 1:
The shielding layer is positioned in advance under the gate clock lines to prevent burnt defects before they occur. By blocking the parasitic capacitance and reducing electrical stress on the gate clock lines, the shielding layer provides protective cushioning that prevents breakdown and safety issues.
Data Source
AI summary
A display device may include a substrate divided into a display area and a non-display area, a gate driving circuit disposed on the substrate and disposed in the non-display area, a plurality of gate clock lines disposed on the substrate and disposed outside the gate driving circuit, a passivation layer disposed on the gate driving circuit and the plurality of gate clock lines, a common electrode disposed on the passivation layer and not overlapping with the plurality of gate clock lines, and a shielding layer located in the non-display area, disposed on the passivation layer, and overlapping with the plurality of gate clock lines.