Semiconductor Shielding Layer Post-Encapsulation Grounding

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Solution Overview

Problem

Existing semiconductor devices face challenges in isolating from electromagnetic interference (EMI) and radio frequency interference (RFI) due to voids and delamination issues when a shielding layer is mounted before encapsulation, which affects device performance.

Innovation Solution

A method involving the deposition of an encapsulant over a semiconductor die and forming channels to expose conductive bumps or interconnect structures, allowing a shielding layer to be mounted over the encapsulant, ensuring electrical connection and reducing interference while preventing voids and delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a shielding layer is mounted before encapsulation, then EMI and RFI isolation is improved, but voids and delamination occur reducing reliability

Engineering Contradiction:
ImproveEMI and RFI isolationVSAvoidbonding between shielding layer and encapsulant
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent inverts the conventional sequence by depositing the encapsulant first and then forming the shielding layer on top of it. This reversal eliminates the interface between the shielding layer and encapsulant that causes delamination, while still providing effective EMI/RFI shielding by grounding the shielding layer through vias that pass through the encapsulant to the substrate ground plane.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The encapsulant is deposited in advance before the shielding layer is formed. This preliminary deposition of the encapsulant creates a stable base that prevents void formation and ensures uniform coverage, allowing the subsequent shielding layer to be properly grounded without causing delamination or voids.

Inventive Principle:
Principle #10Preliminary action

2Object-affected harmful factors

If a shielding layer is mounted before encapsulation, then EMI and RFI isolation is improved, but voids form around the semiconductor die

Engineering Contradiction:
ImproveEMI and RFI isolationVSAvoiduniformity of encapsulant coverage
Core Design Contradiction:
Object-affected harmful factorsVSManufacturing precision

Solution Approach 1:

By reversing the sequence to deposit encapsulant first and then form the shielding layer, the patent eliminates the obstacle that the shielding layer presents to encapsulant flow. This ensures uniform encapsulant coverage over the semiconductor die without voids, while the shielding layer is subsequently formed and grounded through vias.

Inventive Principle:
Principle #13The other way round (Inversion)

3Reliability

If channels are formed to expose conductive bumps after encapsulation, then electrical connection for grounding is improved, but additional manufacturing steps are required

Engineering Contradiction:
Improveelectrical connection of shielding layerVSAvoidnumber of manufacturing steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the grounding connection by forming vias (channels) that pass through the encapsulant layer to reach the conductive bumps on the substrate. This segmentation allows the shielding layer to be electrically connected to ground through discrete vertical pathways, ensuring reliable grounding while integrating seamlessly into the manufacturing process.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The vias (channels) act as intermediaries that connect the shielding layer to the conductive bumps and ultimately to the ground plane. These intermediary structures enable electrical connection through the encapsulant layer without requiring complex rework or additional connection mechanisms.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8350368B2Semiconductor device and method of forming shielding layer after encapsulation and grounded through interconnect structure
Publication Date: 2013.01.08 STATS CHIPPAC MANAGEMENT PTE LTD
  • US8350368B2 patent drawing
  • US8350368B2 patent drawing
  • US8350368B2 patent drawing

AI summary

A method of manufacturing a semiconductor device includes providing a substrate having a conductive bump formed over the substrate and a semiconductor die with an active surface oriented to the substrate. An encapsulant is deposited over the semiconductor die and the conductive bump, and the encapsulant is planarized to expose a back surface of the semiconductor die opposite the active surface while leaving the encapsulant covering the conductive bump. A channel is formed into the encapsulant to expose the conductive bump. The channel extends vertically from a surface of the encapsulant down through the encapsulant and into a portion of the conductive bump. The channel extends through the encapsulant horizontally along a length of the semiconductor die. A shielding layer is formed over the encapsulant and the back surface of the semiconductor die. The shielding layer includes a docking pin extending into the channel and into the portion of the conductive bump to electrically connect to the conductive bump and provide isolation from inter-device interference.