Shielding Pattern for Overlapping Clock Wiring and Gate Pattern
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Solution Overview
Problem
Conventional display apparatuses face challenges in minimizing the bezel area and preventing coupling phenomena between the gate pattern and clock signal wiring, which can lead to performance deterioration and increased power consumption.
Innovation Solution
Incorporating a shielding pattern between the gate pattern and clock signal wiring, applied with a constant voltage, to prevent coupling and reduce the bezel area by overlapping the clock signal wiring with the gate pattern and disposing it on the source pattern, while using connection wiring to transmit the constant voltage to the shielding pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the clock signal wiring is arranged separately from the gate pattern, then coupling phenomena are prevented, but the bezel area increases
Solution Approach 1:
A shielding pattern is introduced as an intermediary element between the gate pattern and the clock signal wiring. This shielding pattern, applied with a constant voltage (e.g., ELVDD or ELVSS), acts as a mediator that prevents direct electromagnetic coupling between the gate pattern and clock signal wiring, allowing them to be closely arranged or overlap in plan view while maintaining signal integrity and preventing harmful coupling phenomena.
2Area of stationary object
If the clock signal wiring overlaps the gate pattern, then the bezel area is reduced, but coupling phenomena occur between the gate pattern and clock signal wiring
Solution Approach 1:
The shielding pattern serves as a protective intermediary layer between the gate pattern and clock signal wiring that overlap in plan view. By applying a constant voltage to the shielding pattern, it creates an electromagnetic shield that prevents coupling phenomena, thereby maintaining signal integrity and device reliability even when the wirings are closely arranged or overlap.
Solution Approach 2:
The solution moves from a two-dimensional planar arrangement to a three-dimensional stacked structure. The clock signal wiring and gate pattern overlap in the plan view (XY plane), but are separated in the vertical dimension (Z plane) by the shielding pattern, which is disposed between them. This dimensional separation allows close packing while preventing coupling.
3Area of stationary object
If wirings are rearranged to reduce bezel area, then the display area is increased, but coupling phenomena between gate pattern and clock signal wiring increase power consumption
Solution Approach 1:
The shielding pattern acts as an energy-isolating intermediary between the gate pattern and clock signal wiring. By blocking electromagnetic coupling, it prevents energy loss and unnecessary power consumption that would result from coupling phenomena, thereby maintaining low power consumption even when wirings are closely arranged to maximize display area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively reduces the bezel area and prevents coupling phenomena, thereby enhancing the display apparatus's performance and reducing power consumption by shielding the gate pattern and clock signal wiring.
Implementation Method 1
a shielding pattern disposed between the gate pattern and the clock signal wiring and applied with a constant voltage
Data Source
AI summary
A display apparatus includes: a display panel; a driving circuit which provides a driving signal to the display panel and includes at least one driving transistor; and a clock signal wiring for providing a clock signal to the driving circuit. The driving circuit includes an active pattern, a gate pattern, a source pattern, and a shielding pattern, the gate pattern overlaps the active pattern in a plan view, a major surface plane of the source pattern is disposed in a layer different from a layer the active pattern is disposed in, the source pattern is electrically connected to the active pattern, the shielding pattern is disposed between the gate pattern and the clock signal wiring and applied with a constant voltage, and the clock signal wiring overlaps the gate pattern in the plan view and is disposed on the source pattern.