Shielding Pattern for Semiconductor Memory Noise Reduction
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Solution Overview
Problem
Current semiconductor memory devices face limitations in increasing the degree of integration and operational reliability due to coupling noise and source line bouncing, which restrict the freedom of upper line arrangement and affect erase efficiency.
Innovation Solution
The semiconductor memory device incorporates a shielding pattern between bit lines and upper lines, with contact plugs connecting the shielding pattern to upper lines, and a manufacturing method involving the formation of bit lines, a common source line, and a pad pattern, followed by the deposition of insulating and shielding layers, to reduce coupling noise and enhance operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bit lines and upper lines are disposed close to each other to improve degree of integration, then device integration is improved, but coupling noise increases
Solution Approach 1:
A shielding pattern is introduced as an intermediary element between the bit lines and upper lines. This shielding pattern acts as a mediator that blocks electromagnetic coupling between the two conductor groups, allowing them to be disposed close together for high integration while preventing noise interference through the shielding effect.
2Object-affected harmful factors
If shielding pattern is added between bit lines and upper lines to reduce coupling noise, then noise reduction is achieved, but device complexity increases
Solution Approach 1:
The shielding pattern is merged with the existing interlayer insulating layer structure. The shielding pattern is formed within the same layer stack as the insulating layers, combining the shielding function with the existing insulation structure rather than adding a completely separate component, thereby reducing overall device complexity.
3Object-affected harmful factors
If contact plugs are formed to connect shielding pattern to upper lines, then shielding effectiveness is improved, but manufacturing complexity increases
Solution Approach 1:
The contact plugs connecting the shielding pattern to the upper lines are formed during the preliminary manufacturing stages, along with the formation of the interlayer insulating layers and bit lines. This preliminary formation of contact plugs integrates the shielding connection into the existing manufacturing flow without requiring additional specialized processing steps.
4Reliability
If upper lines are arranged with freedom from bit lines to improve operational characteristics, then erase efficiency is improved, but device area increases
Solution Approach 1:
The shielding pattern serves as a mediator that enables the upper lines to be arranged freely above the bit lines without being constrained by noise coupling issues. This allows optimization of upper line positions for improved erase efficiency while maintaining compact device area through vertical stacking.
Data Source
AI summary
A semiconductor device includes bit lines and a common source line connected to a memory cell array, wherein the bit lines and the common source line are spaced apart from each other in a first level; a pad pattern spaced apart from the bit lines and the common source line in the first level; a first insulating layer covering the bit lines, the common source line, and the pad pattern; a shielding pattern overlapping with the bit lines and disposed on the first insulating layer; a first upper line and a second upper line spaced apart from each other above the shielding pattern; a plurality of contact plugs extending from the first and second upper lines toward the bit lines, common source line, and pad pattern, wherein one or more of the plurality of contact plugs connect the shielding pattern to the second upper line.