Shielding Polysilicon Sidewall Oxide for Low-Leakage SGT MOSFETs
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Solution Overview
Problem
In shielded gate trench metal-oxide-semiconductor field effect transistors (SGT MOSFETs), high gate-to-source and drain-to-source leakage currents occur due to thin oxide thicknesses in the top region of shielding polysilicon and trench sidewall transition regions when thermal oxide is used for the inter-polysilicon oxide layer.
Innovation Solution
A method is developed to form a shielding polysilicon sidewall protection layer by forming an epitaxial layer on a semiconductor substrate, creating a trench, and depositing a heavily N-type doped polysilicon layer with a transition oxide protection layer, followed by an inter-polysilicon oxide layer to increase oxide thicknesses, using techniques like thermal oxidation and chemical vapor deposition to enhance the oxide layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thermal oxide is used for the inter-polysilicon oxide layer, then the manufacturing process is simple, but the oxide thickness in the top region of shielding polysilicon and trench sidewall transition region becomes thin, causing high leakage current
Solution Approach 1:
The oxide layer formation process is segmented into two distinct parts: a liner oxide layer formed by thermal oxidation and a transition oxide protection layer formed by chemical vapor deposition. This segmentation allows each layer to be optimized for its specific function - the liner oxide provides a thin, high-quality interface layer while the transition oxide provides additional thickness and protection in critical regions, thereby reducing leakage current without overly complicating the manufacturing process
Solution Approach 2:
The patent employs a composite oxide structure consisting of two different oxide layers with different formation mechanisms and properties. The liner oxide layer (thermal oxide) and transition oxide protection layer (CVD oxide) are combined to create a multi-layer structure that leverages the advantages of both materials - the excellent interface quality of thermal oxide and the controllable thickness and protection capabilities of CVD oxide, effectively solving the leakage current problem
2Ease of manufacture
If thermal oxide is used for the inter-polysilicon oxide layer, then the process is straightforward, but the oxide thickness in critical regions becomes insufficient, leading to high gate-to-source and drain-to-source leakage currents
Solution Approach 1:
The oxide formation is divided into two sequential steps with different methodologies. The first step uses thermal oxidation to create a uniform liner oxide layer with precise thickness control. The second step uses chemical vapor deposition to add a transition oxide protection layer specifically in regions where additional thickness is needed. This segmentation enables precise thickness control in critical areas while maintaining process straightforwardness
Solution Approach 2:
The transition oxide protection layer is selectively formed to provide enhanced thickness and protection in specific critical regions - namely the top region of shielding polysilicon and the trench sidewall transition region - while other regions maintain the thinner liner oxide layer. This local quality approach ensures that oxide thickness is optimized precisely where it is most needed to prevent leakage, without unnecessarily increasing thickness or complexity throughout the entire structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate-to-source and drain-to-source leakage currents by increasing the oxide thicknesses, thereby improving the performance and longevity of SGT MOSFETs.
Implementation Method 1
forming a transition oxide protection layer on a surface of the shielding polysilicon; the liner oxide layer and the transition oxide protection layer from a top and sidewall surface of the shielding polysilicon
Implementation Method 2
forming an inter-polysilicon oxide (IPO) layer on the top surface of the shielding polysilicon, the inner sidewall of the trench
Data Source
AI summary
The present application provides a method for forming a sidewall protection layer in a heavily N-type doped shielding polysilicon for reducing gate to source leakage in a shielded gate trench metal-oxide-semiconductor field effect transistor (SGT MOSFET). In the process of forming a shielding polysilicon sidewall is manufactured by using a secondary oxidation layer forming process, so as to increase a thickness of an oxide in a top region of the shielding polysilicon and a thickness of an oxide of a trench sidewall in a transition region between the shielding polysilicon and an N-type doped gate polysilicon to solve the problem of serious gate to source leakage current.