Shielding in Unit Capacitor Array for Linearity

Solution Overview

Problem

Capacitor arrays in integrated circuits face challenges with differential and integral nonlinearity due to unit capacitor mismatch, especially with smaller capacitance values, leading to reduced accuracy and increased power consumption.

Innovation Solution

The design incorporates unit capacitors with isolated and shared nodes in a vertical structure on multiple metal layers, along with a shield node to reduce parasitic capacitance and improve linearity, allowing for smaller capacitance values like 0.1 fF and lower, while maintaining uniformity and reducing routing irregularities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If unit capacitor values are reduced to achieve smaller capacitance values, then power consumption and design area are reduced, but differential and integral nonlinearity increase due to unit capacitor mismatch

Engineering Contradiction:

Improvepower consumptionVSAvoidlinearity accuracy

Core Design Contradiction:

Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

A shield node is introduced as an intermediary element between the isolated capacitor node and surrounding circuit elements. This shield node, when connected to a low impedance node, acts as an electrostatic shield that reduces parasitic capacitance and minimizes the impact of routing irregularities, thereby maintaining linearity accuracy even with smaller capacitor values

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The capacitor structure transitions from a planar configuration to a three-dimensional vertical structure spanning multiple metal layers. The isolated capacitor node is formed in a vertical structure on two or more metal layers, which reduces the footprint area while maintaining the capacitor's electrical characteristics and linearity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If unit capacitor values are reduced to achieve smaller capacitance values, then design area is reduced, but differential and integral nonlinearity increase due to unit capacitor mismatch

Engineering Contradiction:

Improvedesign areaVSAvoidlinearity accuracy

Core Design Contradiction:

Area of stationary objectVSMeasurement precision

Solution Approach 1:

The capacitor structure transitions from a planar configuration to a three-dimensional vertical structure spanning multiple metal layers. The isolated capacitor node is formed in a vertical structure on two or more metal layers, which reduces the footprint area while maintaining the capacitor's electrical characteristics and linearity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

A shield node is introduced as an intermediary element between the isolated capacitor node and surrounding circuit elements. This shield node, when connected to a low impedance node, acts as an electrostatic shield that reduces parasitic capacitance and minimizes the impact of routing irregularities, thereby maintaining linearity accuracy even with smaller capacitor values

Inventive Principle:

Principle #24Intermediary (Mediator)

3Ease of manufacture

If traditional capacitor structures are used, then manufacturing is simpler, but parasitic capacitance and routing irregularities increase

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidparasitic capacitance

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The capacitor structure transitions from a planar configuration to a three-dimensional vertical structure spanning multiple metal layers. The isolated capacitor node is formed in a vertical structure on two or more metal layers, which reduces the footprint area while maintaining the capacitor's electrical characteristics and linearity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

A shield node is introduced as an intermediary element between the isolated capacitor node and surrounding circuit elements. This shield node, when connected to a low impedance node, acts as an electrostatic shield that reduces parasitic capacitance and minimizes the impact of routing irregularities

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the linearity and accuracy of capacitor arrays, enabling the use of smaller unit capacitors, reducing power consumption, and lowering design area and cost, while minimizing parasitic capacitance and irregularities.

Implementation Method 1

Each unit capacitor further includes a shield node formed adjacent to the isolated capacitor node in at least one metal layer in which the isolated capacitor node is formed, the shield node coupled to a low impedance node

Methodology Applied

Scientific EffectElectrostatic shielding: Faraday Cage

Data Source

PatentUS10840232B2Shielding in a unit capacitor array

Publication Date: 2020.11.17 SILICON LABORATORIES INC

AI summary

An array of capacitors on an integrated circuit includes a plurality of unit capacitors. Each unit capacitor includes an isolated capacitor node formed in a pillar structure. Each unit capacitor further includes a shared capacitor adjacent to the isolated capacitor node. The shared capacitor node is electrically coupled to shared capacitor nodes of other unit capacitors in the array. Each unit capacitor further includes a shield node coupled to a low impedance node and formed adjacent to the isolated capacitor node to reduce the chance of capacitance forming between conductors to the isolated nodes and the shared nodes thereby preventing unwanted charge from entering the shared nodes and reducing linearity of the array.