Shift-Add Computation Circuit for Low-Latency Video Transforms
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Solution Overview
Problem
The complexity of circuits used in video compression and decompression processes for DCT, DST, IDCT, and IDST leads to significant delays, necessitating a more efficient computation circuit design.
Innovation Solution
A computation circuit comprising multiple operation circuits and calculation units that selectively shift and process multiplicands based on control signals, utilizing bit valid and sign control signals to generate operation results, and combining these results to minimize delay and circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional computation circuits are used for DCT, DST, IDCT, and IDST operations, then the circuit can perform the required computations, but the circuit complexity becomes large leading to significant delay
Solution Approach 1:
The computation circuit is divided into multiple term operation circuits (first term operation circuit, second term operation circuit, third term operation circuit), each handling specific terms of the computation. This segmentation allows parallel processing of different computational terms, reducing overall computation delay while maintaining functional completeness for DCT, DST, IDCT, and IDST operations.
Solution Approach 2:
The patent transforms the computational approach by introducing bit valid control signals and sign control signals that operate in a control dimension, allowing selective activation of operation circuits based on input characteristics. This dimensional transformation enables the circuit to bypass unnecessary computation paths, reducing delay without sacrificing computational accuracy.
2Productivity
If more operation circuits are added to reduce computation delay, then the productivity improves, but the circuit area increases
Solution Approach 1:
Each term operation circuit is designed with multi-functionality, capable of handling different computational terms (first term, second term, third term) through selective activation via bit valid control signals. This universal design allows the same circuit structure to perform multiple functions, reducing the need for separate dedicated circuits for each term, thereby minimizing overall circuit area while maintaining high operation speed.
Solution Approach 2:
The circuit employs dynamic control through bit valid control signals and sign control signals that adaptively activate or deactivate specific operation circuits based on the input data characteristics. This dynamic behavior allows the circuit to use only the necessary computation paths for each operation, reducing the effective circuit area utilized at any given time while maintaining high productivity when full computation is required.
Data Source
AI summary
A circuit, comprising a first term operation circuit and a second term operation circuit, a third term operation circuit, and a second calculation circuit. Each of the first and the second term operation circuits comprises multiple higher bit operation circuits, a lowest bit operation circuit, and a first calculation circuit. Each of the higher bit operation circuits selectively left-shifts a multiplicand by different bits, outputs the shifted multiplicand, determines a sign of the shifted multiplicand, and left-shifts the shifted multiplicand. The lowest bit operation circuit outputs the multiplicand, and determines a sign of the multiplicand. The first calculation circuit generates a term operation result. The third term operation circuit generates a third term operation result. The second calculation circuit adds the term operation result of the first and second term operation circuits and the third term operation result to generate a total operation result.