Low Gate Count Shift Circuit for Low Power Address Generation
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Solution Overview
Problem
Microcontroller units and mixed signal processors face challenges in achieving low power consumption while maintaining computational performance, as simply limiting address generation operations to reduce power consumption can limit processing speed.
Innovation Solution
The implementation of a low energy accelerator processor circuit with a dedicated load store unit and a low gate count shift circuit that selectively shifts register data by an integer number of bits, avoiding the use of a full barrel shifter to facilitate low-power address generation operations for vector operations like FFT and filtering functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a full barrel shifter is used to support arbitrary bit shifts, then address generation capability is improved, but gate count and energy consumption increase significantly
Solution Approach 1:
The patent segments the shift operation into multiple smaller shift steps. Instead of using a single full barrel shifter for arbitrary bit shifts, the address generation is broken down into sequential shift operations that can be performed by simpler circuitry, reducing the gate count and energy consumption while maintaining the capability to generate arbitrary addresses through multiple steps.
Solution Approach 2:
The patent introduces dynamic address generation mechanisms that adapt the shift amount and strategy based on the specific operation requirements. By dynamically selecting shift amounts and using conditional shift operations, the system achieves full address update capability without requiring a static full barrel shifter, thereby reducing overall energy consumption and gate count.
2Use of energy by moving object
If address generation operations are limited to reduce power consumption, then energy usage decreases, but computational performance and processing speed are reduced
Solution Approach 1:
The patent employs periodic shift operations where shifts are performed in rhythmic intervals rather than continuously. By using conditional execution and selective shift operations that activate only when needed, the system maintains low power consumption while ensuring that address generation keeps pace with computational requirements, thus preserving processing speed.
Solution Approach 2:
The patent changes the parameters of shift operations dynamically, adjusting shift amounts and frequencies based on the computational workload and address generation needs. This allows the system to optimize between power consumption and processing speed by using larger shifts when performance is critical and smaller or fewer shifts when power savings are prioritized.
Data Source
AI summary
Described examples include integrated circuits such as microcontrollers with a low energy accelerator processor circuit or other application specific integrated processor circuit including a load store circuit operative to perform load and store operations associated with at least one register and a low gate count shift circuit to selectively shift the data of the register by only an integer number of bits less than the register data width without using a barrel shifter for low power operation to support vector operations for FFT or filtering functions.