Shift-Frequency Scaling for Scan Pattern Power Management
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Solution Overview
Problem
Existing scan testing methods for digital circuits face challenges in efficiently detecting defects and managing power dissipation, leading to prolonged test times and potential thermal issues due to constant scan shift frequencies that do not account for varying power dissipation across different scan patterns.
Innovation Solution
The method involves determining and optimizing different clock frequencies for sections of a scan pattern set based on power dissipation constraints, allowing each section to be shifted at a frequency that does not exceed the device's power limits, thereby reducing overall test time and managing thermal effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a constant scan shift frequency is used for all scan patterns, then the test application process is simple, but the power dissipation may exceed limits during high-activity patterns and test time is prolonged
Solution Approach 1:
The patent applies dynamics by making the scan shift frequency variable rather than constant. The test system dynamically adjusts the scan shift frequency based on the switching activity level of each scan pattern, allowing higher frequencies for low-activity patterns and lower frequencies for high-activity patterns to maintain power dissipation within limits while optimizing test speed
Solution Approach 2:
The patent changes the frequency parameter adaptively based on scan pattern characteristics. By calculating the switching activity of each pattern and corresponding power dissipation, the system selects appropriate frequency values from a set of predetermined frequencies, thereby optimizing both test efficiency and power management
2Loss of time
If the scan shift frequency is increased to reduce test time, then productivity improves, but power dissipation and thermal effects increase
Solution Approach 1:
The patent adjusts the frequency parameter based on thermal and power constraints. By evaluating the switching activity and estimated power dissipation of each scan pattern, the system selects frequency values that reduce test time while keeping power dissipation and die temperature within acceptable limits
3Device complexity
If a single clock frequency is used for all scan patterns, then device complexity is reduced, but test effectiveness is compromised due to power limits
Solution Approach 1:
The patent segments the scan pattern set into groups based on switching activity levels. Each segment is assigned an appropriate clock frequency from a set of predetermined frequencies, allowing the system to optimize test effectiveness for different pattern types while maintaining manageable device control complexity
Solution Approach 2:
The system dynamically selects clock frequencies based on scan pattern characteristics rather than using a fixed single frequency. This adaptive approach improves test effectiveness by matching frequency to pattern activity while the segmentation strategy keeps control complexity manageable
Data Source
AI summary
There is provided a method that includes, (a) determining a first clock frequency for shifting a first section of a scan pattern set through a path in a digital circuit such that a first power dissipated by the digital circuit while shifting the first section does not exceed a power limit, (b) determining a second clock frequency for shifting a second section of the scan pattern set through the path such that a second power dissipated by the digital circuit while shifting the second section does not exceed the power limit, (c) shifting the first section through the path at the first clock frequency, and (d) shifting the second section through the path at the second clock frequency, where first and second clock frequencies are different from one another. There is also provided a system that performs the method.