Shift-Last MAC Circuit Using Fast Adders to Cut Carry Delay
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Solution Overview
Problem
Existing integrated circuits (ICs) perform shift and add operations during the multiplication step, leading to excessive power consumption, reduced computing speed, and increased transistor usage due to the use of ripple carry adders, which hinder the utilization of fast adders in later stages of the multiplication and accumulation (MAC) process.
Innovation Solution
The ICs perform the shift operation at a later stage (shift last) and utilize fast adders like simplified carry select adders or carry-lookahead adders to sum partial products, reducing carry propagation delay and minimizing power consumption while enhancing computing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If shift and add operations are performed during the multiplication step using ripple carry adders, then the MAC process can be completed, but power consumption increases and computing speed decreases
Solution Approach 1:
The patent segments the MAC process into distinct multiplication and accumulation stages. The multiplication step generates partial products without immediate addition, allowing the use of fast adders only when needed. This segmentation enables better resource utilization and reduces unnecessary power consumption from continuous adder operations.
Solution Approach 2:
The patent inverts the conventional approach by performing accumulation before final addition rather than adding during multiplication. The partial products are generated first, then accumulated, and only then added using fast adders. This reversal eliminates the need for ripple carry adders during the multiplication phase, reducing power consumption while maintaining computing speed.
2Productivity
If ripple carry adders are used during multiplication, then addition can be performed, but the number of transistors increases
Solution Approach 1:
The patent divides the computational process into multiplication and accumulation phases, using different adder architectures for each. Ripple carry adders are eliminated from the multiplication phase entirely, and fast adders are used only in the accumulation phase where they are more efficient. This segmentation reduces the total transistor count while maintaining full computing capability.
Solution Approach 2:
The patent changes the operational parameters of the MAC process by delaying the addition operation until after multiplication is complete. This parameter change allows the use of fast adders with fewer transistors compared to ripple carry adders, reducing device complexity while preserving computing capability through optimized timing and architecture.
3Productivity
If ripple carry adders are used in the MAC process, then addition operations can be performed, but carry propagation delay increases
Solution Approach 1:
The patent inverts the conventional MAC process by separating multiplication and accumulation into distinct stages. Addition using fast adders is performed after multiplication completes, rather than during the multiplication step. This inversion eliminates the carry propagation delay issue entirely, as fast adders are used only in the accumulation phase where they can operate without the timing constraints that plague ripple carry adders during multiplication.
Data Source
AI summary
A method for performing a shift last multiplication and accumulation (MAC) process. A processing circuit can multiply a first input by a first bit of a second input to obtain a first intermediate output. The processing circuit can multiply a third input by a first bit of a fourth input to obtain a second intermediate output. The processing circuit can sum the first and second intermediate outputs to obtain a first sum. The processing circuit can multiply the first input by a second bit of the second input to obtain a third intermediate output. The processing circuit can multiply the third input by a second bit of the fourth input to obtain a fourth intermediate output. The processing circuit can sum the third and fourth intermediate outputs to obtain a second sum. The processing circuit can generate an output by accumulating the first sum and the second sum.