Reduced-Level Shift Overflow Detection Unit for DSP Processors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The computation of shift overflow conditions in DSP processors is a timing critical path, limiting the speed of shift instructions, especially when executed in a single cycle, due to the complexity of saturation detection in left-shift with saturation operations.
Innovation Solution
A reduced-level shift overflow detection unit is introduced, which divides the 32-bit shift data word into sets and uses encoded shift amount signals to detect overflow conditions independently of conventional shifter operations, reducing the number of logic levels involved in the computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional saturation detection is used in left-shift with saturation operations, then overflow detection accuracy is maintained, but the number of logic levels increases, limiting processor operating frequency
Solution Approach 1:
The patent divides the 32-bit shift data word into multiple sets (e.g., four 8-bit sets) and processes each set independently through separate overflow detection sub-units. This segmentation reduces the logic levels required for each individual detection unit while maintaining overall detection accuracy through combination of results.
Solution Approach 2:
The patent transforms the traditional sequential overflow detection approach into a parallel structure by introducing multiple overflow detection sub-units that operate simultaneously on different bit sets. This dimensional change from sequential to parallel processing reduces the critical path and logic levels in the timing critical path.
2Productivity
If single-cycle shift instruction execution is implemented, then instruction execution speed is improved, but the complexity of timing critical path increases due to saturation detection requirements
Solution Approach 1:
By segmenting the shift data into multiple independent sets and processing them through separate sub-units, the patent enables single-cycle execution while distributing the computational complexity across parallel paths, thereby reducing the complexity of any single timing critical path.
Solution Approach 2:
The patent performs overflow detection in parallel with the shift operation itself, rather than sequentially after completion. The overflow detection sub-units begin their computation simultaneously with the shifter operation, allowing both to complete within the same cycle and reducing overall critical path complexity.
Data Source
AI summary
A processor includes a shift overflow detector for rapidly detecting overflows that may result during execution of a shift instruction. Shift indication signals are generated in response to changes in logic state between adjacent pairs of bits of a received shift data word. A received shift amount is decoded to produce decoded shift signals that indicate an amount of shifting for the received shift data word. An overflow condition is detected in response to the generated shift indication signals and the decoded shift signals and an indication of the detected overflow condition is provided.