Shift Register 6T1C Structure for Gate Driver Circuit
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Solution Overview
Problem
Current gate driver circuits in display technologies face challenges in reducing production costs and manufacturing complexity, particularly due to the complexity of pixel driving circuits with 7T1C structures, which hinder the improvement of display resolution.
Innovation Solution
A shift register and gate driver circuit design with a 6T1C structure, incorporating specific transistor and capacitor configurations, and a driving method that allows for efficient transmission of scan signals to pixel driving circuits, reducing the number of elements and simplifying the circuit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 7T1C structure is used in pixel driving circuits, then signal control accuracy is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts the clock signal transmission function from the pixel driving circuit into a dedicated shift register circuit. By separating the clock signal path from the data signal path, the patent reduces the complexity of the pixel driving circuit while ensuring accurate signal control through specialized clock signal management in the shift register.
Solution Approach 2:
The patent introduces a shift register as an intermediary circuit between the gate driver and the pixel circuits. This shift register acts as a buffer that manages clock signal distribution, thereby simplifying the overall system architecture while maintaining precise signal control through dedicated clock signal stages.
2Reliability
If a 7T1C structure is used in pixel driving circuits, then signal control accuracy is improved, but manufacturing cost and process difficulty increase
Solution Approach 1:
The patent segments the gate driver circuit into distinct functional modules: a main driver circuit and a shift register circuit with multiple clock signal stages. This segmentation allows for standardized manufacturing of modular components, simplifying the overall manufacturing process while maintaining signal control accuracy through dedicated clock signal management pathways.
Solution Approach 2:
The patent changes the operational parameters by introducing multiple clock signal stages (first clock signal, second clock signal, third clock signal) with different timing characteristics. This parameter differentiation enables precise control of signal transmission timing, improving reliability while the modular structure facilitates easier manufacturing through parameterized design.
3Area of moving object
If the number of transistors and capacitors is reduced to 6T1C, then area occupied by pixel circuits is reduced, but signal transmission reliability may be compromised
Solution Approach 1:
The patent merges the clock signal generation and distribution functions into the shift register circuit, combining multiple clock signal stages in a compact configuration. This merging approach reduces the overall area by eliminating redundant components while maintaining signal transmission reliability through integrated clock signal management that ensures proper timing control.
Solution Approach 2:
The patent transitions from a planar 7T1C configuration to a multi-dimensional 6T1C structure by introducing time-multiplexed clock signal stages. The shift register uses sequential clock signals (first, second, third clock signals) to manage signal transmission, effectively adding a temporal dimension that compensates for the reduced component count and maintains reliability with smaller area.
Data Source
AI summary
A shift register includes: a first input sub-circuit configured to transmit a first clock signal to a first node in response to an input signal and a first voltage signal; a first output sub-circuit configured to transmit a second voltage signal to a first output signal terminal under control of a voltage of the first node; a second input sub-circuit configured to transmit the input signal to a second node in response to the first clock signal; and, a second output sub-circuit configured to transmit the first voltage signal to the first output signal terminal under control of a voltage of the second node. A voltage value of one of the first voltage signal and the second voltage signal is greater than that of a reference voltage, and a voltage value of another one is less than that of the reference voltage.