Shift Register Unit AC Drive Leakage Suppression
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Solution Overview
Problem
In display technology, shift register units in gate driver circuits experience drift and reduced reliability due to leakage currents in polycrystalline silicon TFTs when operated for long periods or at high temperatures, affecting the normal operation and power consumption.
Innovation Solution
The proposed solution involves a shift register unit design with specific node control units and clock signal management, utilizing alternating current (AC) to prevent leakage currents and enhance response speed, including separate outputting of carry and gate driving signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If direct current (DC) is applied to the TFT for a long time period or the TFT operates at a high temperature, then the TFT experiences drift and reduced reliability, but applying alternating current (AC) instead increases reliability and prevents drift
Solution Approach 1:
The patent applies periodic alternating current (AC) signals to the TFT gates instead of continuous direct current (DC). The AC signals periodically switch between high and low levels, preventing charge accumulation and leakage current buildup that occur with DC operation. This periodic action eliminates drift in polycrystalline silicon TFTs while maintaining reliable operation over extended time periods.
2Productivity
If polycrystalline silicon TFTs are used in the shift register unit, then the device can operate, but leakage current increases and power consumption increases
Solution Approach 1:
The patent employs periodic AC driving signals that periodically turn the TFTs on and off, preventing continuous leakage current flow. By using alternating current instead of direct current, the TFTs operate in a switching mode rather than a continuous conduction mode, significantly reducing leakage current and associated power consumption while maintaining operational capability.
3Device complexity
If the gate driving signal serves as a carry signal for an adjacent level shift register unit, then the circuit structure is simplified, but the response speed becomes relatively small
Solution Approach 1:
The patent segments the signal output functions by providing separate output terminals for gate driving signals and carry signals. This segmentation allows the gate driving signal and carry signal to be independently optimized and transmitted through separate pathways, eliminating the speed bottleneck that occurs when the gate driving signal must also serve as the carry signal for the next stage.
4Reliability
If a relatively large drift occurs for the TFT, then the reliability is reduced, but preventing drift requires AC operation which affects the normal DC-biased circuit design
Solution Approach 1:
The patent changes the fundamental operating parameter of the TFTs from direct current (DC) bias to alternating current (AC) signaling. This parameter change transforms the TFT operation from a continuous conduction mode prone to drift to a switching mode that prevents charge accumulation. The AC operation mode fundamentally alters how the TFTs function, eliminating drift without requiring additional complex circuitry.
Data Source
AI summary
A shift register unit, a driving method thereof, a gate driver circuit and a display device are provided. The shift register unit includes a first pull-up node control unit, a second pull-up node control unit configured to enable a pull-up node to be at a first level at a pull-down maintenance stage under the control of a first clock signal, a first pull-down node control unit configured to enable a pull-down node to be at a second level at the pull-down maintenance stage under the control of the first clock signal, a second pull-down node control unit, a gate driving signal output unit configured to output a gate driving signal under the control of the pull-up and pull-down nodes, and a carry signal output unit configured to enable a carry signal output end to output a carry signal under the control of the pull-up and pull-down nodes.