Shift Register Unit With Adjustable Signal Duration
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Solution Overview
Problem
Existing gate driving circuits in display technology cannot adjust the effective duration of their output gate driving signal according to actual needs, which is necessary for optimal performance, especially when threshold voltages of driving transistors drift over time.
Innovation Solution
A shift register unit with specific circuits and a driving method that allows for adjustable signal duration, including an input circuit, charging circuit, inverter circuit, output circuit, and pull-down circuit, connected in a cascaded arrangement with clock signal lines, enabling dynamic adjustment of signal duration through sequential stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the gate driving circuit uses a fixed signal duration design, then the circuit structure is simple, but the adaptability to different threshold voltage conditions deteriorates
Solution Approach 1:
The patent applies dynamics by making the signal duration adjustable rather than fixed. The gate driving circuit incorporates multiple charging stages (first charging stage and second charging stage) that can be selectively activated to extend the high-level signal duration. This dynamic adjustment allows the circuit to adapt to threshold voltage drift in driving transistors while maintaining a relatively simple overall structure based on standard shift register units.
Solution Approach 2:
The patent segments the charging process into multiple stages. The first charging stage charges the holding capacitor during the normal shift operation, while the second charging stage provides additional charging to extend the signal duration. This segmentation allows flexible control over the output signal width without requiring a complete redesign of the circuit architecture.
2Adaptability or versatility
If the signal duration is extended to accommodate threshold voltage drift, then the adaptability improves, but the circuit complexity increases
Solution Approach 1:
The patent achieves multi-functionality by designing the second clock signal terminal to serve dual purposes: it controls the input circuit for signal transmission and simultaneously controls the charging circuit for extending signal duration. The holding capacitor also serves multiple functions by maintaining the high-level signal during both the first and second charging stages. This universal design allows signal duration adjustment without proportionally increasing circuit complexity.
3Duration of action of moving object
If multiple charging stages are added to adjust signal duration, then the signal adaptability improves, but the device complexity increases
Solution Approach 1:
The patent merges the clock signal distribution function and the signal duration control function into a single clock signal terminal structure. The first and second clock signal terminals provide clock signals that simultaneously control both the signal shifting operation and the multi-stage charging process. This merging reduces the need for separate control circuits and minimizes overall device complexity while achieving adjustable signal duration.
Data Source
AI summary
The present disclosure relates to the field of display technology, and provides a shift register unit and a driving method thereof, a gate driving circuit, and a display panel. The shift register unit includes: an input circuit, a charging circuit, an inverter circuit, an output circuit, and a pull-down circuit. The input circuit is connected to a second clock signal terminal, a signal input terminal and a first node. The inverter circuit is connected to the signal input terminal, the second clock signal terminal, a first power supply terminal, a second power supply terminal and a pull-down node. The output circuit is connected to the pull-up node, the first power supply terminal and an output terminal. The pull-down circuit is connected to the pull-down node, the second power supply terminal, the pull-up node, and the output terminal.