Shift Register Circuit for Reversible and All-Gate Line Driving
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Solution Overview
Problem
Conventional shift registers are unable to simultaneously drive all gate lines and change the driving direction of gate lines, which is necessary in certain liquid crystal display devices.
Innovation Solution
A shift register design that includes multiple stages with scan pulse, carry pulse, and all-drive signal output units, controlled by voltage states and external signals, allowing for simultaneous all-drive signal supply to gate lines during an all-drive period and sequential scan pulse supply forwardly or reversely during a scan period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional shift register is used to sequentially supply scan pulses to gate lines, then the gate lines can be driven in order, but it cannot simultaneously drive all gate lines or change the driving direction of gate lines
Solution Approach 1:
The shift register is divided into multiple stages, with each stage containing independent control nodes (set node, reset node, control node) and output units (scan pulse output unit, all-drive signal output unit). This segmentation allows each stage to be independently controlled, enabling flexible switching between sequential scanning mode and simultaneous all-drive mode, as well as forward and reverse driving directions.
Solution Approach 2:
The patent implements dynamic control of the shift register stages through external control signals that change the voltage states of control nodes in real-time. The set nodes, reset nodes, and control nodes can be dynamically switched between different voltage levels (first voltage level, second voltage level) based on the required driving mode, allowing the system to adapt between sequential and simultaneous driving, and between forward and reverse directions.
2Productivity
If the shift register supplies scan pulses sequentially to gate lines, then the structure remains simple, but it cannot supply all-drive signals to all gate lines simultaneously
Solution Approach 1:
Each stage of the shift register is designed with dual functionality: it can output scan pulses sequentially through the scan pulse output unit, or output all-drive signals simultaneously through the all-drive signal output unit. The same stage structure and control nodes serve both functions, allowing the system to achieve simultaneous driving capability without proportionally increasing the overall device complexity.
Solution Approach 2:
The control nodes (set node, reset node, control node) are prepared in advance with specific voltage states to pre-condition each stage for its intended operation mode. By setting the voltage levels of these control nodes before the driving operation, the shift register stages are pre-configured to either output scan pulses or all-drive signals, enabling rapid switching between sequential and simultaneous driving modes without complex real-time control logic.
Data Source
AI summary
A shift register is disclosed. The shift register includes a plurality of stages for sequentially outputting scan pulses, wherein each of the stages includes a scan pulse output unit controlled according to voltage states of a set node and reset node for outputting a corresponding one of the scan pulses and supplying the corresponding scan pulse to a corresponding gate line, a carry pulse output unit controlled according to the voltage states of the set node and reset node for outputting a carry pulse and supplying it to an upstream one of the stages and a downstream one of the stages, a first node controller for controlling the voltage states of the set node and reset node according to a carry pulse from the upstream stage, a carry pulse from the downstream stage and a first control signal externally supplied thereto, an all-drive signal output unit controlled according to voltage states of a control node and reset control node for outputting an all-drive signal and supplying it to the corresponding gate line, and a second node controller for controlling the voltage states of the control node and reset control node according to the voltage state of the set node, the voltage state of the reset node, and a start pulse and second control signal externally supplied thereto.