Shift Register Circuit for AMOLED Gate Drive Signal Generation
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Solution Overview
Problem
Existing shift register units in AMOLED display devices require multiple components to generate two gate drive signals, leading to complex structures and increased layout space and fabrication costs, while also compromising signal stability.
Innovation Solution
A shift register unit is designed with a shift register circuit and an inverting circuit, utilizing transistors and capacitors to delay and invert input signals based on clock signals, allowing for the generation of two gate drive signals in a simplified structure, reducing layout space and fabrication costs, and enhancing signal stability through a latch circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple components are used to generate two gate drive signals, then the signal generation capability is improved, but the circuit structure becomes complex and layout space increases
Solution Approach 1:
The patent combines the functions of multiple components into a single shift register unit that can generate two gate drive signals (first output signal and second output signal) simultaneously. The shift register circuit integrates the input circuit, latch circuit, and output circuit into one unified structure, eliminating the need for separate components for each signal generation function.
Solution Approach 2:
The shift register unit is designed with multi-functionality to serve multiple purposes: it receives input signals, generates clock signals, latches voltages, and outputs both first and second gate drive signals with different phases. This universal design allows one component to perform what previously required multiple specialized components.
2Adaptability or versatility
If multiple components are used to generate two gate drive signals, then the signal generation capability is improved, but fabrication costs increase
Solution Approach 1:
By merging multiple components into a single shift register unit, the patent reduces the total number of fabrication steps and material layers required. The integrated design allows for simpler manufacturing processes and lower fabrication costs compared to assembling multiple separate components.
3Adaptability or versatility
If multiple components are used to generate two gate drive signals, then the signal generation capability is improved, but signal stability deteriorates
Solution Approach 1:
The patent employs an inverting circuit that generates the second output signal by inverting the first output signal. This inversion approach ensures that the two gate drive signals have complementary phases (first phase and second phase), which is critical for stable OLED pixel operation. The latch circuit maintains stable voltage levels at intermediate nodes, preventing signal instability.
4Area of stationary object
If a simplified structure is used, then layout space is reduced, but signal stability may be compromised
Solution Approach 1:
The patent achieves space reduction by merging multiple functions into a compact shift register unit with integrated circuits. The layout space is minimized while maintaining signal stability through the careful design of the latch circuit and inverting circuit, which ensure proper signal levels and phases are maintained despite the reduced physical footprint.
Data Source
AI summary
A shift register unit and a drive method thereof, a gate drive circuit, and a display device are disclosed. The shift register unit includes a shift resister circuit which delays a phase of an input signal from an input terminal to output a first output signal from a first output terminal and an inverting circuit which generates an inverting signal having an inverted voltage with respect to the first output signal and output it from a second output terminal. The shift resister circuit includes a first input circuit configured to control a voltage of a first node, a second input circuit configured to control a voltage of a second node, a latch circuit configured to latch the voltage of the first node and that of the second node as being inverted, and a first output circuit configured to selectively output the second clock signal or a first voltage.


