Daisy-Chain Shift Register Layout for Lower Area and Dynamic Current
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Solution Overview
Problem
Shift registers require a large circuit area and high dynamic current consumption due to the number of flip-flops, which increases with the number of stages.
Innovation Solution
A shift register design with a pre-stage and N shift-stages configured in a daisy-chain form, where odd-numbered stages have a first circuit structure and even-numbered stages have a second circuit structure, utilizing a clock division circuit to output divided clock signals, reducing transistor count and optimizing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of flip-flops is increased to accommodate more stages in the shift register, then the data storage capacity and shifting capability are improved, but the circuit area and dynamic current consumption increase significantly
Solution Approach 1:
The shift register is divided into multiple stages, where each stage processes one bit of data. By segmenting the overall function into discrete stages that operate in sequence, the design achieves high data storage capacity while keeping each individual stage compact, thus reducing the total circuit area compared to parallel implementations.
Solution Approach 2:
The shift register uses clocked operation where data moves through stages periodically with each clock cycle. This periodic action allows the same circuit structure to be reused across multiple stages, reducing the overall circuit area while maintaining the ability to store and shift multiple bits of data through time-multiplexed operation.
2Quantity of substance
If the number of flip-flops is increased to accommodate more stages in the shift register, then the data storage capacity and shifting capability are improved, but the dynamic current consumption increases
Solution Approach 1:
By dividing the shift register into sequential stages that process data one bit at a time, the dynamic current consumption is distributed across time rather than occurring simultaneously across all stages. This segmentation reduces peak current draw while maintaining the ability to store and shift multiple bits through sequential operation.
Solution Approach 2:
The clocked, periodic operation of each stage ensures that dynamic current is consumed only during active switching transitions rather than continuously. This allows multiple bits to be stored using the same physical circuitry activated at different time intervals, reducing overall dynamic power consumption compared to parallel structures where all stages would consume current simultaneously.
3Reliability
If traditional flip-flop based shift register design is used, then reliable data storage and shifting is achieved, but the circuit complexity and area increase with the number of stages
Solution Approach 1:
The patent uses a standardized stage template that can be copied and replicated across multiple stages. Each stage follows the same circuit pattern, which simplifies the overall design process and reduces complexity while maintaining reliable data storage and shifting functionality across all stages through consistent, proven circuit architecture.
Data Source
AI summary
A shift register includes a pre-stage configured to output a pre-voltage signal based on a clock signal and a reset signal, and “N” shift-stages configured to receive the clock signal, and output “N” output signals, respectively. The pre-stage and the “N” shift-stages are coupled in a daisy-chain form. Odd-numbered shift-stages among the “N” shift-stages are configured with the same first circuit structure, and even-numbered shift-stages among the “N” shift-stages are configured with the same second circuit structure.