Shift Register Circuit Area Reduction Stability
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Solution Overview
Problem
The challenge in reducing the size of shift register circuitry for liquid crystal displays (LCDs) lies in maintaining circuit stability, which makes it difficult to minimize the thickness and frame width of the display.
Innovation Solution
The proposed shift register design includes an Nth stage shift register unit, an (N+1)th stage shift register unit, a first control unit, and a first auxiliary pull-down unit, with shared driving control voltage and clock signals to generate gate signals, allowing for reduced area and extended high-level driving control voltage time, thereby reducing the overall size and maintaining stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of the shift register circuitry is reduced, then the thickness and frame width of the display are reduced, but the circuit stability deteriorates
Solution Approach 1:
The patent merges the pull-up unit of the Nth stage shift register with the pull-down unit of the (N+1)th stage shift register into a shared resource. This consolidation reduces the total number of transistors and circuit area while maintaining stable voltage control through coordinated switching of the merged units, thereby resolving the contradiction between area reduction and stability maintenance.
Solution Approach 2:
The patent implements multi-functionality by designing the pull-up unit to serve dual purposes: it acts as the pull-up unit for the Nth stage and simultaneously serves as the pull-down unit for the (N+1)th stage. This universal design reduces redundancy and circuit area while ensuring that voltage control stability is maintained through proper timing and control signal coordination.
2Area of stationary object
If the shift register area is reduced, then the display frame width is reduced, but the driving control voltage high-level time is insufficient
Solution Approach 1:
The patent applies preliminary action by having the pull-up unit of the Nth stage begin charging the gate line voltage in advance before the (N+1)th stage requires it. The shared pull-up unit is controlled with timing signals that ensure the voltage reaches the required high level duration, thereby extending the effective high-level time without increasing circuit area.
Solution Approach 2:
The patent ensures continuity of useful action by coordinating the operation of the shared pull-up unit across stage transitions. The control signals are designed to maintain continuous voltage supply and charging action, preventing gaps in the high-level voltage duration while the pull-up unit serves multiple stages, thus extending the effective driving control voltage high-level time without area expansion.
Data Source
AI summary
A shift register for providing a plurality of gate signals includes an Nth stage shift register unit and an (N+1)th stage shift register unit. The Nth stage shift register unit includes a first pull up unit, a first driving unit, a first control unit and a first auxiliary pull down unit. The (N+1)th stage shift register unit includes a second pull up unit, a second driving unit, a first pull down unit and a second auxiliary pull down unit. The first and second pull up units are both coupled to the first and second driving units for controlling the first and second driving units to generate gate signals. The first and second auxiliary pull down units are both coupled to the first control unit for pulling down the gate signals.