2D Shift Register Array for Versatile Image Processing
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Solution Overview
Problem
Traditional image processors either consume high energy due to their versatile software development capabilities or are limited in functionality due to custom-designed fixed function circuitry, lacking a balance between versatility and power efficiency.
Innovation Solution
A two-dimensional shift register array structure coupled with an execution lane array allows for efficient data shifting and processing across multiple execution lanes, providing a versatile and power-efficient image processing solution by moving large data amounts into register space for direct processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general purpose processor with vector instruction enhancements is used, then versatile application software development platform is provided, but larger amounts of energy are consumed per unit of data during execution
Solution Approach 1:
The processor is divided into multiple execution lanes (e.g., 8 lanes) that can operate in parallel, each handling a portion of the image data. This segmentation allows the system to process data more efficiently by distributing the workload across multiple dedicated paths, reducing the energy overhead associated with general-purpose instruction execution while maintaining software versatility through programmable control.
Solution Approach 2:
The execution lanes are dynamically configured through software control to handle different image processing tasks. The system can adapt the number of active lanes, the size of data blocks processed per lane, and the specific operations performed based on the application requirements. This dynamic reconfiguration allows the system to optimize energy consumption for each specific task while maintaining broad versatility.
2Use of energy by moving object
If fixed function hardwired circuitry is applied to larger blocks of data, then power consumption per unit of data is reduced, but limited set of tasks that the processor is able to perform results
Solution Approach 1:
The execution lanes are designed with universal registers and control logic that can be programmed to perform multiple different image processing functions. Each execution lane contains general-purpose registers that can be configured through software to handle various tasks such as convolution, edge detection, or color space conversion. This universality allows the system to achieve the power efficiency of dedicated hardware while maintaining the versatility of software-based processing.
Solution Approach 2:
Instead of using completely different hardware circuits for different tasks, the system uses multiple copies of the same execution lane structure. These identical lanes can be programmed to perform different functions by loading different data and control values, eliminating the need for multiple specialized hardware circuits while maintaining task diversity and power efficiency.
3Productivity
If two dimensional shift register array structure is used for data shifting, then efficient data handling and processing across multiple execution lanes is enabled, but device complexity increases
Solution Approach 1:
The register array and execution lanes are merged into a single integrated structure where the registers serve dual purposes: storing data for processing and providing the data to execution lanes through systematic shifting. This merging eliminates the need for separate data storage and transfer mechanisms, reducing overall device complexity while maintaining efficient data handling across all execution lanes.
Data Source
AI summary
An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.