Shift Register With Asymmetric Clock Signals For Display

The patent divides the single clock signal system into two independent clock signals (first clock signal and second clock signal) with different duty ratios. This segmentation allows the sampling and holding operations to be performed using different clock phases, preventing the skew and slop issues that occur when using a single clock signal and its inverted version. The two clock signals are generated independently to avoid the harmful effects of signal inversion delays.

The patent employs asymmetric duty ratios for the two clock signals used in the sampling and holding circuits. The first clock signal has a duty ratio different from the second clock signal, creating an asymmetric timing relationship that prevents simultaneous transitions and eliminates the skew-induced malfunction. This asymmetric design ensures that the sampling and holding operations do not interfere with each other despite the presence of skew or slop.

The patent extracts and removes unnecessary transistors from the conventional four-stack structure. By eliminating redundant switching elements, the design reduces the number of stacked transistors between the power supply voltages. This extraction of unnecessary components directly reduces the voltage drop across the stack and decreases power consumption while preserving the essential sampling and holding functionality through the optimized two-clock signal approach.

The patent changes the structural parameter of the transistor stack from four stacked transistors to a reduced configuration. By modifying the number of transistors in the stack, the voltage drop and power consumption parameters are improved. The parameter change maintains the functional requirements for sampling and holding operations while optimizing the electrical characteristics for lower energy loss.