Shift Register With Asymmetric Gate Electrode Overlap
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Solution Overview
Problem
The power consumption of gate driving circuits in liquid crystal display devices, particularly in GIP type devices, is high due to the large parasitic capacitance of amorphous silicon TFTs in the output buffer units, leading to greater energy usage compared to polysilicon TFT-based devices.
Innovation Solution
A shift register design with a switching device structure where the gate electrode overlaps with a first electrode area that is 10–15% smaller than the area where it overlaps with a second electrode, reducing parasitic capacitance and power consumption by optimizing the layout of sub-electrodes and their connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon TFT is used in the output buffer unit, then the gate driving circuit can be mounted in the panel (GIP type), but the parasitic capacitance is large resulting in high power consumption
Solution Approach 1:
The patent applies local quality by making the overlap area between the gate electrode and first electrode (source electrode) smaller than the overlap area between the gate electrode and second electrode (drain electrode). This asymmetric design locally reduces the parasitic capacitance at the input side where the clock pulse is applied, thereby reducing power consumption while maintaining the amorphous silicon TFT's manufacturing advantages
Solution Approach 2:
The patent changes the geometric parameters of the TFT structure by creating an asymmetric overlap configuration. Specifically, the first area (gate-to-source overlap) is reduced to 10-15% less than the second area (gate-to-drain overlap), which directly reduces the parasitic capacitance value and consequently the power consumption according to the formula P=CV²f
2Device complexity
If the gate electrode overlaps equally with both first and second electrodes, then the structure is symmetric and simple, but the parasitic capacitance is maximized increasing power consumption
Solution Approach 1:
The patent directly applies asymmetry by designing the gate electrode overlap areas to be unequal. The first area (gate-to-source overlap) is intentionally made smaller than the second area (gate-to-drain overlap) by 10-15%, creating an asymmetric structure that reduces parasitic capacitance at the critical input side while maintaining overall structural simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces power consumption by 10–15% and minimizes noise instability caused by fast clock pulse frequencies, enhancing the efficiency of the shift register.
Implementation Method 1
the TFT of the output buffer unit has a greatest size in the gate driving circuit, resulting to have a greatest capacitance C of a parasitic capacitor generated between a gate electrode and a first electrode (source electrode) which receives the clock pulse in the TFT
Data Source
AI summary
The present invention relates to a shift register in which a structure of a switching device of an output buffer unit is changed for reducing power consumption. The shift register includes a plurality of stages each having a plurality of switching devices, for forwarding a scan pulse in succession, wherein the at least one of the plurality of switching device has a first area at which a gate electrode thereof overlaps with a first electrode thereof with a size different from a second area at which the gate electrode overlaps with a second electrode thereof.