Shift Register Auxiliary Module Selective Clock Input
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Solution Overview
Problem
Existing shift register circuits in liquid crystal display panels consume high power due to constant clock signal input, leading to reduced yield rates.
Innovation Solution
The shift register circuit is enhanced with an auxiliary module that selectively inputs clock signals only during scanning, maintaining a low potential state during other periods, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock signals are input constantly to the shift register circuit, then the shift register can operate continuously and output scanning signals, but the power consumption increases and yield rate decreases
Solution Approach 1:
The patent applies periodic action by controlling the clock signal to be input only during specific periods when scanning signals need to be output. The clock signal terminal receives clock signals during active scanning periods and maintains a low potential state during inactive periods, creating a periodic input pattern that reduces power consumption while ensuring continuous operation capability when needed
Solution Approach 2:
The patent implements dynamics by making the clock signal input state changeable - it can switch between receiving clock signals and maintaining a low potential state based on operational requirements. This dynamic control allows the system to adapt between active scanning mode (higher power) and idle mode (lower power), resolving the contradiction between continuous operation and power consumption
2Reliability
If clock signals are input constantly to the shift register circuit, then the scanning function is maintained, but the yield rate of display panels is reduced
Solution Approach 1:
The patent uses periodic action to input clock signals only during periods when scanning signals need to be output reliably. By synchronizing clock signal input with scanning operations and maintaining low potential during non-scanning periods, the system ensures scanning stability when active while reducing overall power consumption to improve yield rate
Data Source
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AI summary
A shift register, a gate electrode drive circuit, a display panel, and a display apparatus, the shift register comprising: an input module (01), used for outputting a signal of a signal input terminal (Input) to a first node (P1); a reset module (02), used for outputting a signal of a signal reset terminal (Reset) to the first node (P1); an output module (03), used for outputting a signal of the first node (P1) to a scanning signal output terminal (Out); a buffering module (04), used for outputting a signal of the first node (P1) to a trigger signal terminal (STV); an auxiliary module (05), used for outputting to a second node (P2) a high voltage signal inputted by a clock signal terminal (CLK), the second node (P2) controlling a control output module (03) to output a scanning signal to a scanning signal output terminal (Out). By means of the addition of the auxiliary module (05), the shift register, when outputting a scanning signal, selects an input clock signal, and can thereby reduce the power consumption of the shift register, thus improving the yield of the display panel.