Shift Register Unit Bias Control for Threshold Voltage Stability
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Solution Overview
Problem
The existing gate drive circuits in display devices suffer from threshold voltage loss due to long-term forward bias of pull-down transistors, leading to abnormal output and reduced service life of shift register units.
Innovation Solution
Incorporating a first bias control circuit that manages the bias state of pull-down transistors by changing the clock signal levels between display and non-display phases, ensuring the transistors are in a reverse bias state during non-display phases to alleviate threshold voltage loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pull-down transistors are kept in forward bias state during display phase, then scanning signal output is maintained, but threshold voltage loss occurs leading to abnormal output and reduced service life
Solution Approach 1:
The patent applies periodic action by switching the pull-down transistor between forward bias state during display phase and reverse bias state during non-display phase. This periodic switching prevents continuous forward bias, thereby reducing threshold voltage loss and extending transistor service life while maintaining normal scanning signal output functionality.
2Reliability
If clock signal level is changed between display and non-display phases, then bias state of pull-down transistor is controlled, but circuit complexity increases
Solution Approach 1:
The patent implements dynamics by making the clock signal level variable between display phase (first level) and non-display phase (second level). This dynamic clock signal control enables automatic switching of pull-down transistor bias state without requiring additional complex control circuits, thus achieving threshold voltage stability with minimal added complexity.
Data Source
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AI summary
A shift register unit, a method for driving a shift register unit, a gate drive circuit, and a display device are provided. The shift register unit (100) includes a display circuit (1), and the display circuit (1) is configured to provide a drive scanning signal to a corresponding gate line in a display phase, and the display circuit (1) includes a first control circuit (11) and a first bias control circuit (12). The first control circuit (11) is configured to perform noise reduction on an output terminal (OT) of the display circuit (1) under control of a level of the first node (a). The first bias control circuit (12) is configured to transmit a first reference voltage signal provided by the first reference voltage signal terminal (Vref1) to the first node (a) under control of a first clock signal provided by the first clock signal terminal (CLK1), thereby turning off the first control circuit (11) by controlling the level of the first node (a) in a non-display phase. The shift register unit (100) can alleviate the threshold voltage change caused by the reason that the pull-down transistor is in a forward bias state for a long time during the display phase, thereby ensuring the normal output of the shift register unit.