Bi-directional Shift Register Minimizing Transistor Bias Stress
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Solution Overview
Problem
Conventional bi-directional shift registers suffer from bias stress on transistors due to high voltage levels applied to the gate, leading to aging issues.
Innovation Solution
A shift register design that includes a scan direction controller, node controllers, an output unit, and discharge circuit units to manage voltage levels and enable signals, ensuring that each stage is enabled by signals from adjacent stages, and includes additional discharge mechanisms to minimize bias stress by discharging voltages effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If high voltage levels are applied to the gate of transistors in conventional bi-directional shift registers, then the shift register can operate bi-directionally with proper signal levels, but bias stress accumulates on transistors leading to aging issues
Solution Approach 1:
The patent introduces a bootstrapping capacitor as an intermediary element that stores voltage information and transfers it between stages. This capacitor acts as a mediator that enables voltage level translation without directly applying high stress voltages to the transistor gates, thereby reducing bias stress while maintaining bi-directional operation capability
Solution Approach 2:
The patent dynamically changes voltage parameters by using different voltage levels (Vdd, Vss, and intermediate levels) at different operational phases. By controlling the timing and magnitude of voltage applications to the bootstrapping capacitor and transistor gates, the system achieves bi-directional operation while minimizing the duration and magnitude of high voltage stress on transistors
2Reliability
If additional discharge circuit units are added to minimize bias stress, then transistor reliability improves, but device complexity increases
Solution Approach 1:
The bootstrapping capacitor serves multiple functions simultaneously: it stores voltage information for signal transmission, enables voltage level translation for bi-directional operation, and acts as a discharge path to minimize bias stress on transistors. This multi-functionality reduces the need for separate dedicated discharge circuits, thereby limiting the increase in device complexity
Solution Approach 2:
The patent merges the voltage storage function, voltage translation function, and bias stress relief function into a single integrated bootstrapping mechanism. By combining these functions that could have been implemented as separate circuits, the overall device complexity is minimized while still achieving improved transistor reliability
Data Source
AI summary
A shift register minimizing bias stress applied to transistors is disclosed. A shift register including n stages outputting scan pluses that are sequentially delayed in a forward or reverse direction thereof, where n is positive integer and wherein each stage includes: a scan direction controller that provides a first or second voltage to a scan direction control node according to a first or second enable signal and controlling the forward or reverse direction output; a first node controller that controls a first node according to a voltage on the scan direction control node; a second node controller that controls a second node according to the voltage on the scan direction control node and a voltage on the first node; an output unit that outputs a clock signal as scan pulse according to voltages on the first and second nodes; a third node controller that provides one of the first and second voltages to a third node according to the first and second enable signals; a first discharge circuit unit that discharges the voltage on the first node according to voltages of the second and third nodes; and a second discharge circuit unit that discharges the voltage on the third node according to one of a third enable signal and a fourth enable signal.