Shift Register Black Frame Insertion for High Refresh Displays
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Solution Overview
Problem
Current display technologies face limitations in achieving high refresh frequencies due to the limited number of black frame insertions, leading to identification abnormalities in application scenarios like scanning codes or taking pictures, as they struggle to support the required refresh rates for such demanding tasks.
Innovation Solution
A shift register design that includes an input circuit, control circuits, and an output circuit, which transmits multiple signals to increase the frequency of black frame insertions by outputting high-level signals more frequently, thereby enhancing the refresh frequency of the display panel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional shift register designs are used, then the circuit structure is simple, but the refresh frequency is limited due to limited black frame insertions
Solution Approach 1:
The shift register is divided into multiple independent stages, each capable of generating black frame insertion signals. This segmentation allows parallel operation of multiple stages to increase the overall frequency of black frame insertions without requiring a complete redesign of the entire circuit system.
Solution Approach 2:
The shift register employs periodic clock signals to control the sequential operation of its stages, creating regular intervals for black frame insertion. By optimizing the period and phase of clock signals across different stages, the circuit achieves higher refresh frequencies through coordinated periodic black frame insertions.
2Productivity
If the frequency of black frame insertions is increased, then the refresh frequency improves, but the circuit complexity increases
Solution Approach 1:
Multiple functional blocks within the shift register are merged into a unified cascaded structure where stages share common control mechanisms and signal paths. This merging allows the circuit to achieve high refresh frequencies through coordinated operation without proportionally increasing overall complexity.
Solution Approach 2:
Each stage of the shift register is designed with universal functionality to handle both data shifting and black frame insertion control. This multi-functionality allows the same circuit structure to serve multiple purposes, increasing refresh frequency capabilities without requiring additional dedicated circuits for each function.
Data Source
AI summary
A shift register includes: an input circuit transmitting a first signal to a first node in response to a first clock signal and a second signal, transmitting the second signal to the first node in response to the first clock signal and the first signal; a first control circuit transmitting the first clock signal to a second node in response to the first node, transmitting a first voltage to the second node in response to the first clock signal; a second control circuit transmitting a second voltage to a third node in response to the first node, transmitting a second clock signal to the third node in response to the second node and the second clock signal; an output circuit transmitting the first voltage to a signal output terminal in response to the first node, transmitting the second voltage to the signal output terminal in response to the third node.