Shift Register Black Frame Insertion for OLED Smearing
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Solution Overview
Problem
Dynamic image smearing occurs in OLED display panels when switching frames, affecting display quality and requiring a solution to enhance Moving Picture Response Time (MPRT) while maintaining high refresh frequency.
Innovation Solution
A shift register with integrated sub-circuits for display pre-charge reset, sensing pre-charge reset, pull-down control, output, sensing cascade, and black frame insertion cascade, which allows for simultaneous black frame insertion across multiple rows, reducing the time required for writing black data and maintaining high refresh frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If black frame insertion is performed to reduce dynamic image smearing, then MPRT is enhanced, but refresh frequency must be reduced exponentially which affects display quality
Solution Approach 1:
The shift register is divided into multiple independent stages, each capable of autonomous operation. This segmentation allows different stages to perform different functions simultaneously - some stages write display data while others write black data, enabling parallel processing that reduces the impact on refresh frequency
Solution Approach 2:
The circuit performs pre-charge operations before the actual data writing phase. By pre-charging nodes and preparing the circuit state in advance, the black frame insertion can be executed more efficiently without extending the overall frame time, thus preserving refresh frequency
2Reliability
If black frame insertion is performed row by row, then dynamic image smearing is reduced, but the time required for writing black data increases
Solution Approach 1:
Multiple shift register stages are merged into a single cascaded system that can process multiple rows simultaneously. The cascade structure allows black frame insertion to be performed across multiple rows in parallel, significantly reducing the total time required compared to sequential row-by-row processing
Solution Approach 2:
The circuit maintains continuous operation during black frame insertion by utilizing the cascaded structure to keep multiple stages active simultaneously. While one stage is writing black data to one row, other stages are writing to other rows, ensuring continuous productive action without idle time
3Reliability
If refresh frequency is reduced to allow black frame insertion, then dynamic image smearing is reduced, but display quality deteriorates
Solution Approach 1:
The display panel is segmented into multiple zones corresponding to different shift register stages, allowing simultaneous black frame insertion in some zones while maintaining normal operation in others. This segmentation enables partial optimization without compromising overall display quality
Solution Approach 2:
Black frame insertion is applied partially rather than uniformly across all rows. By selecting specific rows for black frame insertion based on the cascaded stage structure, the circuit achieves dynamic image smearing reduction in critical areas while maintaining high refresh frequency and display quality overall
Data Source
AI summary
A shift register, a gate drive circuit and a driving method therefor. The shift register includes a display pre-charge reset subcircuit, a sensing pre-charge reset subcircuit, a pull-down control subcircuit, an output subcircuit, a sensing cascade subcircuit and a black frame insertion cascade subcircuit. The display pre-charge reset subcircuit is configured to provide a signal of a first power supply end for a pull-up node under control of a first signal input end and provide a signal of a second power supply end to the pull-up node under control of a reset signal end; the sensing pre-charge reset subcircuit is configured to provide a signal of a first clock signal end to the pull-up node under control of the sensing cascade node and the first clock signal end, and provide a signal of the second power supply end to the pull-up node under control of a total reset end.