Shift Register Circuit Black Image Insertion for OLED Smear

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Solution Overview

Problem

OLED display apparatuses suffer from image smear, specifically dynamic image smear, during the process of switching dynamic pictures, which is not effectively addressed by existing technologies.

Innovation Solution

A shift register circuit is designed with an input sub-circuit, an output sub-circuit, a first voltage boosting sub-circuit, and a control sub-circuit, which work together to manage input signals, clock signals, and voltages to reduce image smear by implementing a black image insertion process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional shift register circuits are used for driving OLED displays, then the basic scanning function is achieved, but dynamic image smear occurs during picture switching

Engineering Contradiction:
Improveimage display qualityVSAvoiddynamic image smear
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by inserting a black image frame between consecutive color image frames before the actual display. The shift register circuit generates scanning signals that activate the display apparatus in a specific sequence: first displaying a black image, then transitioning to the color image. This preliminary black image insertion allows the light-emitting elements to be fully turned off before the next color image is displayed, eliminating dynamic image smear by ensuring complete light emission cessation between frames.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If black image insertion process is implemented to reduce image smear, then MPRT function is improved, but device complexity increases

Engineering Contradiction:
Improvelight-emitting durationVSAvoidcircuit structure
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent applies universality by designing the shift register circuit to perform multiple functions using the same basic components. The shift register circuit generates scanning signals for both the black image insertion process and the subsequent color image display. The same shift register stages, timing control units, and voltage boosting circuits are utilized to control both the black frame insertion timing and the color image scanning, eliminating the need for separate dedicated circuits for each function and thus minimizing the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of operation

If conventional driving methods are used, then simple circuit operation is maintained, but image smear problem persists

Engineering Contradiction:
Improvedriving method simplicityVSAvoidimage quality
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent applies feedback by implementing a timing control unit that receives feedback signals from the shift register circuit and adjusts the scanning signal generation accordingly. The timing control unit monitors the state of the shift register stages and dynamically controls the timing of scanning signals to ensure proper synchronization between the black image insertion and color image display phases. This feedback mechanism maintains ease of operation by automating the complex timing coordination, while ensuring reliable image quality by preventing any overlap between black and color image display periods.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12236915B2Shift register circuit, gate driver circuit and driving method therefor, and display apparatus
Publication Date: 2025.02.25 HEFEI BOE ZHUOYIN TECH CO LTD
  • US12236915B2 patent drawing
  • US12236915B2 patent drawing
  • US12236915B2 patent drawing

AI summary

A shift register circuit includes an input sub-circuit, an output sub-circuit and a control sub-circuit. The input sub-circuit is coupled to a first input signal terminal and a pull-up node, and configured to, under control of a first input signal, transmit the first input signal to the pull-up node. The output sub-circuit is at least coupled to the pull-up node, a first clock signal terminal and a first signal output terminal, and configured to transmit a first clock signal to the first signal output terminal under control of a voltage at the pull-up node. The control sub-circuit is coupled to at least one first reference node, at least one first control signal terminal and the pull-up node, and configured to transmit a voltage at a first reference node to the pull-up node under control of a first control signal.