Shift Register Unit for OLED Gate Driving Circuit

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Solution Overview

Problem

Existing gate driving circuits face challenges in outputting scan and sense driving signals with different periods and pulse widths during display and blanking periods in OLED display panels, requiring a complex structure with many transistors and capacitors, which complicates achieving high PPI (Pixels Per Inch) with minimal components.

Innovation Solution

A shift register unit with an input circuit, first and second control circuits, blanking control circuit, and output circuits, where the blanking control circuit controls both nodes to output driving signals for two rows of pixel circuits, reducing the number of transistors and capacitors, and simplifying the circuit design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate control circuits are used for each node to output scan and sense driving signals with different periods and pulse widths, then the driving signals can be output accurately, but the number of transistors and capacitors increases, complicating the circuit structure

Engineering Contradiction:
Improvedriving signal output accuracyVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines two separate control circuits into a single shared blanking control circuit that controls both the first node and second node. This merging reduces the number of transistors and capacitors while still enabling accurate output of scan and sense driving signals with different periods and pulse widths by using one circuit to manage both nodes' timing requirements

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The blanking control circuit is designed to perform multiple functions: it controls both the first node and second node, manages different time periods (display and blanking periods), and generates different pulse widths for scan and sense signals. This multi-functionality allows one circuit to replace what would traditionally require separate dedicated circuits for each function

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If more transistors and capacitors are used to achieve high PPI with minimal components, then the display resolution can be improved, but the frame size and cost increase

Engineering Contradiction:
ImprovePPI (Pixels Per Inch)VSAvoidframe size
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

By merging the control circuits for the first node and second node into a single shared blanking control circuit, the patent reduces the overall component count. This reduction in transistors and capacitors directly decreases the frame size while maintaining the high PPI requirement, as fewer components occupy less physical space in the gate driving circuit

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11244595B2Shift register unit comprising input circuit, first control circuit, blanking control circuit, first output circuit, and second output circuit, driving method, gate driving circuit, and display device
Publication Date: 2022.02.08 HEFEI BOE ZHUOYIN TECH CO LTD
  • US11244595B2 patent drawing
  • US11244595B2 patent drawing
  • US11244595B2 patent drawing

AI summary

A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit. The input circuit is configured to control a level of a first node in response to an input signal input; the first control circuit is configured to control a level of the second node in response to the input signal and the level of the first node; the blanking control circuit is configured to control the level of the first node and the level of the second node; the first output circuit is configured to output a first output signal at the first output terminal; and the second output circuit is configured to output a second output signal at the second output terminal.