Shift Register Circuit With Boosting Mechanism For Power Reduction
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Solution Overview
Problem
Conventional shift register circuits for gate line driving in display apparatuses face challenges in reducing power consumption while maintaining high driving capacity, particularly due to capacitive coupling currents caused by overlap capacitance, which restricts the enlargement of display area.
Innovation Solution
The proposed shift register circuit design includes a pull-up driving circuit with a boosting mechanism and a pull-down driving circuit, where the clock signal is not supplied to the first transistor with a large gate width, reducing capacitive coupling currents and power consumption by utilizing transistors with small gate width for improved driving capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate width of the first transistor is made wide to improve driving capability, then the driving capacity is improved, but the overlap capacitance increases causing higher power consumption
Solution Approach 1:
The patent divides the transistor control function into two separate transistors: a first transistor with small gate width for low-power operation and a second transistor with large gate width for high-drive capability. This segmentation allows each transistor to be optimized for its specific function, resolving the contradiction between driving capacity and power consumption.
Solution Approach 2:
Different transistors are assigned different gate widths according to their specific functional requirements. The first transistor uses a small gate width to minimize overlap capacitance and power consumption, while the second transistor uses a large gate width to provide high driving capability when needed, achieving local optimization of device properties.
2Speed
If the gate width of the first transistor is made wide to improve driving capability, then the charging speed is improved, but the capacitive coupling current increases
Solution Approach 1:
The patent segments the transistor functionality into two separate devices with different gate widths. The first transistor with small gate width handles the low-power switching function, while the second transistor with large gate width handles the high-speed charging function, thereby eliminating the harmful capacitive coupling current while maintaining charging speed.
Solution Approach 2:
The harmful overlap capacitance effect is extracted and isolated to only the second transistor, which is activated only when needed for high-speed charging. The first transistor operates without this harmful effect, achieving a balance between speed and reducing harmful capacitive coupling currents.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves low power consumption and high driving capacity, enabling larger display areas without the limitations imposed by capacitive coupling currents, thereby enhancing the performance of shift register circuits in gate line driving applications.
Implementation Method 1
a first transistor for charging an output terminal by providing a constant first power supply potential to the output terminal
Implementation Method 2
a second transistor for discharging the output terminal
Implementation Method 3
a boosting circuit for increasing a potential at the first node connected to a control electrode of the first transistor
Data Source
AI summary
A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal.