Shift Register Circuit Bootstrap Buffer for Low Power Gate Driving
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Solution Overview
Problem
Conventional gate drivers with single conductivity transistors face challenges in reducing power consumption and increasing driving capability, particularly when performing high-speed falling of gate line voltage, which leads to increased power consumption and data crosstalk due to through current and the need for multiple clock signals.
Innovation Solution
The proposed shift register circuit incorporates a bootstrap buffer unit and a clock-driven timing generation unit, utilizing transistors and capacitors to manage clock signals efficiently, reducing through current and power consumption while enabling high-speed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional gate drivers with single conductivity transistors are used to perform high-speed falling of gate line voltage, then the falling speed is improved, but power consumption increases due to through current
Solution Approach 1:
The gate driver is divided into two independent drivers (first gate driver and second gate driver) that operate on alternating half-cycles of the clock signal. This segmentation allows each driver to control the falling and rising phases separately, eliminating the through current path that causes high power consumption while maintaining fast switching speeds.
Solution Approach 2:
The gate driver operates using periodic clock signals (CLK and /CLK) that alternate between high and low states. The first gate driver operates during one half-cycle while the second gate driver operates during the other half-cycle, creating a periodic operation pattern that eliminates continuous through current flow while maintaining high-speed performance.
2Duration of action of moving object
If multiple clock signals are used to extend selection period for overlap scanning, then the selection period is extended, but device complexity increases
Solution Approach 1:
Two clock signals (CLK and /CLK) serve multiple functions: they control the timing of both gate drivers, enable overlap scanning operation, and automatically extend the selection period through their alternating phases. This multi-functionality achieves extended selection duration without proportionally increasing device complexity.
Solution Approach 2:
The clock signal generation and timing control functions are merged into a unified system where the complementary clock signals (CLK and /CLK) simultaneously control both gate drivers. This merging allows the selection period to be extended through coordinated operation rather than requiring separate independent control circuits for each function.
3Power
If large transistors and capacitors are used to drive large loads at high speed, then driving capability is improved, but area requirements increase
Solution Approach 1:
The load driving function is segmented between two gate drivers that operate alternately. Each driver handles only half of the switching cycle, allowing the use of smaller transistors and capacitors in each driver while collectively maintaining the capability to drive large loads at high speed. This segmentation reduces the area requirement compared to a single large driver.
Data Source
AI summary
Provided is a shift register circuit including a single conductive transistor which performs overlap scanning without increasing the number of clock signals and reduces power consumption by avoiding an ineffective through current, a gate driver, and a display apparatus. The shift register circuit includes: a shift register unit having a first output transistor which connects an output terminal and a first power supply; and a first gate control circuit of which an output terminal is connected to a gate terminal of the first output transistor, wherein the first gate control circuit includes a timing generation unit and a buffer unit, the buffer unit is a bootstrap circuit, and an output of the timing generation unit to which an input signal is inputted is used as an input of the buffer unit and an output of the buffer unit is used as an output of the first gate control circuit.