Shift Register Unit Bootstrap Control for Narrow Pulse Widths

The patent implements dynamic control of transistor conduction states through multi-stage timing. The first transistor is controlled to conduct during a first time period, while the second transistor conducts during a second time period, creating dynamic temporal separation of signal transmission paths. This dynamic timing control allows the circuit to adapt to narrow pulse widths by sequentially activating different transistors rather than requiring simultaneous conduction, thereby maintaining signal integrity despite reduced pulse duration.

The patent introduces a third transistor as an intermediary element that couples the second transistor to either a first potential or second potential based on the conduction state of the first transistor. This intermediary transistor acts as a buffer that isolates the output stage from direct influence by the input signal variations, thereby stabilizing the driving capability. When the first transistor conducts, the third transistor is controlled to connect to a potential that maintains proper voltage levels at the output node, preventing signal degradation even as pixel density increases and pulse widths narrow.

The patent implements preliminary charging of a capacitance connected to the output node before the gate driving signal is fully transmitted. The first transistor is controlled to conduct during a first time period that precedes or overlaps with the signal transmission period, thereby pre-establishing proper voltage levels and charging the output capacitance. This preliminary action ensures that when the narrow pulse signal arrives, the output node is already in a state ready to reliably transmit the signal, compensating for the reduced time available during the narrowed pulse width and maintaining transmission reliability despite increased scanning speed.